公开(公告)号：US08496158B2

公开(公告)日：2013-07-30

申请号：US13604641

申请日：2012-09-06

申请人： Fei Zong ,  Guoliang Gong ,  Meiquan Huang ,  Hejin Liu

发明人： Fei Zong ,  Guoliang Gong ,  Meiquan Huang ,  Hejin Liu

IPC分类号： B23K31/02

CPC分类号： B23K20/007 ,  B23K31/125 ,  H01L24/48 ,  H01L24/78 ,  H01L24/85 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/78301 ,  H01L2224/85 ,  H01L2224/85205 ,  H01L2224/85399 ,  H01L2224/859 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/207

摘要： A method for monitoring free air ball (FAB) formation during a wire bonding process includes attaching a dummy bond wire to an unused location on a first surface of a semiconductor chip carrier, extending the dummy bond wire a predetermined distance from the first surface such that a tip of the dummy bond wire is spaced from the first surface, and forming a dummy FAB at the tip of the bond wire. A profile of the dummy FAB is inspected with an imaging unit to identify any defects in the dummy FAB. An alarm is triggered and the wire bonding process is halted if the dummy FAB is defective so that bonding parameters may be adjusted. The wire bonding process is restarted after the bonding parameters have been adjusted.

摘要翻译： 一种用于在引线接合过程中监测自由空气球（FAB）形成的方法包括将虚拟接合线附接到半导体芯片载体的第一表面上的未使用位置，将虚拟接合线从第一表面延伸预定距离，使得 虚拟接合线的尖端与第一表面间隔开，并且在接合线的尖端处形成虚拟FAB。 用成像单元检查虚拟FAB的轮廓以识别虚拟FAB中的任何缺陷。 如果虚拟FAB有缺陷，则触发报警并停止接线过程，从而可以调整接合参数。 接合参数调整后重新开始引线接合处理。

公开(公告)号：US08907464B2

公开(公告)日：2014-12-09

申请号：US13848734

申请日：2013-03-22

申请人： Huan Wang ,  Meiquan Huang ,  Hejin Liu

发明人： Huan Wang ,  Meiquan Huang ,  Hejin Liu

IPC分类号： H01L23/02 ,  H01L23/04 ,  H01L23/34 ,  H01L23/48 ,  H05K1/18 ,  H05K1/14 ,  H05K3/28

CPC分类号： H05K1/181 ,  H01L23/13 ,  H01L23/3121 ,  H01L25/065 ,  H01L2924/0002 ,  H05K1/0284 ,  H05K1/141 ,  H05K1/144 ,  H05K3/284 ,  H05K2201/041 ,  H05K2201/09027 ,  H05K2201/09118 ,  H05K2203/1316 ,  Y02P70/611 ,  H01L2924/00

摘要： A three dimensional (3D) package includes a helix substrate having a columnar part including a top surface, a bottom surface and a sidewall, and a plurality of steps arranged along the sidewall of the columnar part in the form of a helix. Semiconductor integrated circuits (dies) may be attached on supporting surfaces of the steps. The columnar part, the steps and the dies can be covered with a mold compound. I/Os are formed at either the sides of the steps and/or the top and/or bottom of the columnar part.

摘要翻译： 三维（3D）封装包括具有包括顶表面，底表面和侧壁的柱状部分的螺旋衬底和沿着螺旋形式的柱状部分的侧壁布置的多个台阶。 半导体集成电路（模具）可以附接在台阶的支撑表面上。 柱状部分，台阶和模具可以用模具复合物覆盖。 I / O形成在台阶的两侧和/或柱状部分的顶部和/或底部。

公开(公告)号：US08524529B2

公开(公告)日：2013-09-03

申请号：US13170208

申请日：2011-06-28

申请人： Meiquan Huang ,  Hejin Liu ,  Hanmin Zhang

发明人： Meiquan Huang ,  Hejin Liu ,  Hanmin Zhang

IPC分类号： H01L21/00

CPC分类号： H01L24/49 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48475 ,  H01L2224/48992 ,  H01L2224/48997 ,  H01L2224/4917 ,  H01L2224/85385 ,  H01L2224/85399 ,  H01L2224/85951 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/48455 ,  H01L2924/20753

摘要： An electrical connection includes a first wire having one end stitch bonded to a surface, such as the lead finger of a lead frame or the connection pad of a substrate. A second wire has a first end attached to the surface on a first side of the first wire and a second end attached to the surface on a second, opposing side of the first wire. The second wire acts as a brace that prevents the first wire from lifting off of the surface. If necessary, a third wire can be added that, like the second wire, acts as a brace to prevent the first wire from lifting off of the surface.

摘要翻译： 电连接包括具有结合到表面的一个端部针迹的第一线，例如引线框架的引线指或基底的连接垫。 第二线具有附接到第一线的第一侧上的表面的第一端和附接到第一线的第二相对侧上的表面的第二端。 第二线作为支架，防止第一线从表面脱落。 如果需要，可以添加第三线，其与第二线相似，用作支架以防止第一线从表面上脱离。

公开(公告)号：US20140146497A1

公开(公告)日：2014-05-29

申请号：US13848734

申请日：2013-03-22

申请人： Huan Wang ,  Meiquan Huang ,  Hejin Liu

发明人： Huan Wang ,  Meiquan Huang ,  Hejin Liu

IPC分类号： H05K1/18

CPC分类号： H05K1/181 ,  H01L23/13 ,  H01L23/3121 ,  H01L25/065 ,  H01L2924/0002 ,  H05K1/0284 ,  H05K1/141 ,  H05K1/144 ,  H05K3/284 ,  H05K2201/041 ,  H05K2201/09027 ,  H05K2201/09118 ,  H05K2203/1316 ,  Y02P70/611 ,  H01L2924/00

摘要： A three dimensional (3D) package includes a helix substrate having a columnar part including a top surface, a bottom surface and a sidewall, and a plurality of steps arranged along the sidewall of the columnar part in the form of a helix. Semiconductor integrated circuits (dies) may be attached on supporting surfaces of the steps. The columnar part, the steps and the dies can be covered with a mold compound. I/Os are formed at either the sides of the steps and/or the top and/or bottom of the columnar part.

摘要翻译： 三维（3D）封装包括具有包括顶表面，底表面和侧壁的柱状部分的螺旋衬底和沿螺旋形式的柱状部分的侧壁布置的多个台阶。 半导体集成电路（模具）可以附接在台阶的支撑表面上。 柱状部分，台阶和模具可以用模具复合物覆盖。 I / O形成在台阶的两侧和/或柱状部分的顶部和/或底部。

公开(公告)号：US20120326288A1

公开(公告)日：2012-12-27

申请号：US13489462

申请日：2012-06-06

申请人： Meiquan Huang ,  Hejin Liu ,  Zhijie Wang ,  Dehong Ye ,  Hanmin Zhang

发明人： Meiquan Huang ,  Hejin Liu ,  Zhijie Wang ,  Dehong Ye ,  Hanmin Zhang

IPC分类号： H01L21/56 ,  H01L23/495

CPC分类号： H01L23/49582 ,  H01L21/4832 ,  H01L23/3107 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/131 ,  H01L2224/16245 ,  H01L2224/16258 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2924/00

摘要： A method of assembling a semiconductor device includes providing a conductive lead frame panel and selectively half-etching a top side of the lead frame panel to provide a pin pads. A flip chip die is attached and electrically connected to the pin pads and then the lead frame panel and die are encapsulated with molding compound. A second selective half etching step is performed on a backside of the lead frame panel to form a plurality of separate input/output pins. The side walls of each input/output pin include arcuate surfaces in cross-section.

摘要翻译： 一种组装半导体器件的方法包括：提供导电引线框架面板，并选择性地半导体蚀刻引线框架面板的顶侧以提供引脚焊盘。 连接倒装芯片并电连接到引脚焊盘，然后将引线框架板和模具用模塑料封装。 在引线框板的背面执行第二选择性半蚀刻步骤，以形成多个单独的输入/输出引脚。 每个输入/输出销的侧壁包括横截面的弧形表面。

公开(公告)号：US08288847B2

公开(公告)日：2012-10-16

申请号：US12830446

申请日：2010-07-06

申请人： Meiquan Huang ,  Hejin Liu ,  Wenjian Xu ,  Dehong Ye

发明人： Meiquan Huang ,  Hejin Liu ,  Wenjian Xu ,  Dehong Ye

IPC分类号： H01L23/02

CPC分类号： H01L24/49 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49531 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/48 ,  H01L25/0655 ,  H01L2224/2919 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/48247 ,  H01L2224/49 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/0665 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A dual die semiconductor package has a grid array of electrical contacts on a bottom surface of a substrate. There is a first semiconductor die with a base surface mounted to an upper surface of the substrate and the first semiconductor die has first die upper surface external electrical connection pads on an upper surface that are electrically connected to respective electrical contacts of the grid array. There is also a second semiconductor die with a base surface mounted to an upper surface of a lead frame flag. There are second die upper surface external electrical connection pads on an upper surface of the second semiconductor die. The dual die semiconductor package includes leads and at least some of the leads are electrically connected to respective pads that provide the second die upper surface external electrical connection pads. A package body at encloses the first semiconductor die and the second semiconductor die. The electrical contacts of the grid array and part of each of the leads protrude from the package body to form external package electrical connections. Also, at least part of a base surface of the lead frame flag directly under the second semiconductor die is left exposed by the package body and provides a heat sink.

摘要翻译： 双模半导体封装在基板的底表面上具有电触点的格栅阵列。 存在第一半导体管芯，其具有安装到基板的上表面的基面，并且第一半导体管芯具有电连接到栅格阵列的相应电触点的上表面上的第一管芯上表面外部电连接焊盘。 还有第二半导体管芯，其基面安装在引线框标志的上表面。 在第二半导体管芯的上表面上具有第二管芯上表面外部电连接焊盘。 双模半导体封装包括引线，并且至少一些引线电连接到提供第二管芯上表面外部电连接焊盘的相应焊盘。 封装体包围第一半导体管芯和第二半导体管芯。 栅格阵列的电触点和每个引线的一部分从封装主体突出以形成外部封装电连接。 此外，直接位于第二半导体管芯下方的引线框标志的基面的至少一部分被封装体暴露并提供散热器。

公开(公告)号：US20120077316A1

公开(公告)日：2012-03-29

申请号：US13170208

申请日：2011-06-28

申请人： Meiquan HUANG ,  Hejin Liu ,  Hanmin Zhang

发明人： Meiquan HUANG ,  Hejin Liu ,  Hanmin Zhang

IPC分类号： H01L21/60

CPC分类号： H01L24/49 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48475 ,  H01L2224/48992 ,  H01L2224/48997 ,  H01L2224/4917 ,  H01L2224/85385 ,  H01L2224/85399 ,  H01L2224/85951 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/48455 ,  H01L2924/20753

摘要： An electrical connection includes a first wire having one end stitch bonded to a surface, such as the lead finger of a lead frame or the connection pad of a substrate. A second wire has a first end attached to the surface on a first side of the first wire and a second end attached to the surface on a second, opposing side of the first wire. The second wire acts as a brace that prevents the first wire from lifting off of the surface. If necessary, a third wire can be added that, like the second wire, acts as a brace to prevent the first wire from lifting off of the surface.

摘要翻译： 电连接包括具有结合到表面的一个端部针迹的第一线，例如引线框架的引线指或基底的连接垫。 第二线具有附接到第一线的第一侧上的表面的第一端和附接到第一线的第二相对侧上的表面的第二端。 第二线作为支架，防止第一线从表面脱落。 如果需要，可以添加第三线，其与第二线相似，用作支架以防止第一线从表面上脱离。

公开(公告)号：US20150357266A1

公开(公告)日：2015-12-10

申请号：US14554064

申请日：2014-11-26

申请人： Huan Wang ,  Hejin Liu ,  Weiping Sun

发明人： Huan Wang ,  Hejin Liu ,  Weiping Sun

IPC分类号： H01L23/495 ,  H01L23/31 ,  H01L21/78 ,  H01L21/48 ,  H01L21/56

CPC分类号： H01L23/49555 ,  H01L21/4825 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/4951 ,  H01L23/4952 ,  H01L23/49537 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45686 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00014

摘要： A packaged semiconductor device is assembled using a first lead frame upon which a die is mounted and encapsulated and a second lead frame that provides bent leads for the device. By using two different lead frames, an array of the first lead frames can be configured with more lead frames for more devices than a comparably sized lead frame array of the prior art because the first lead frame array does not need to provide the leads for the packaged devices. Instead, the leads are provided by the second lead frame array, which can be attached to the first lead frame array after the dies have been mounted and encapsulated on the first lead frame array.

摘要翻译： 使用第一引线框架组装封装的半导体器件，在其上安装和封装管芯，以及提供用于器件的弯曲引线的第二引线框架。 通过使用两个不同的引线框架，与现有技术的相当尺寸的引线框架阵列相比，第一引线框架的阵列可以配置有比用于更多器件的更多引线框架，因为第一引线框架阵列不需要为 包装设备。 相反，引线由第二引线框架阵列提供，其可以在管芯已经被安装并封装在第一引线框架阵列上之后附接到第一引线框架阵列。

公开(公告)号：US09209119B1

公开(公告)日：2015-12-08

申请号：US14554064

申请日：2014-11-26

申请人： Huan Wang ,  Hejin Liu ,  Weiping Sun

发明人： Huan Wang ,  Hejin Liu ,  Weiping Sun

IPC分类号： H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31

CPC分类号： H01L23/49555 ,  H01L21/4825 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/4951 ,  H01L23/4952 ,  H01L23/49537 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45686 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00014

摘要： A packaged semiconductor device is assembled using a first lead frame upon which a die is mounted and encapsulated and a second lead frame that provides bent leads for the device. By using two different lead frames, an array of the first lead frames can be configured with more lead frames for more devices than a comparably sized lead frame array of the prior art because the first lead frame array does not need to provide the leads for the packaged devices. Instead, the leads are provided by the second lead frame array, which can be attached to the first lead frame array after the dies have been mounted and encapsulated on the first lead frame array.

摘要翻译： 使用第一引线框架组装封装的半导体器件，在其上安装和封装管芯，以及提供用于器件的弯曲引线的第二引线框架。 通过使用两个不同的引线框架，与现有技术的相当尺寸的引线框架阵列相比，第一引线框架的阵列可以配置有比用于更多器件的更多引线框架，因为第一引线框架阵列不需要为 包装设备。 相反，引线由第二引线框架阵列提供，其可以在管芯已经被安装并封装在第一引线框架阵列上之后附接到第一引线框架阵列。