Chip carrier with reduced interference signal sensitivity
    9.
    发明授权
    Chip carrier with reduced interference signal sensitivity 有权
    具有降低干扰信号灵敏度的芯片载体

    公开(公告)号:US07911026B2

    公开(公告)日:2011-03-22

    申请号:US11618172

    申请日:2006-12-29

    IPC分类号: H01L21/02

    摘要: Carrier including: a substrate having a first interface with first contact holes, and a second interface, which lies opposite the first interface, with second contact holes. The substrate includes a substrate body and electrically conductive contact channels formed therein, wherein each of the contact channels electrically conductively connects a first contact hole to a second contact hole. The carrier also includes a front-side wiring layer arranged on the first interface and; has a first front-side metallization layer formed therein such that it includes a first capacitor electrode for electrically connecting microelectronic devices and/or circuits to a first pole of a signal or supply voltage. The first capacitor electrode, at least partly via a capacitor dielectric formed in the carrier, couples capacitively to electrically conductive regions of a second front-side metallization layer and/or the substrate which at least partly form a second capacitor electrode for electrically connecting the microelectronic devices and/or circuits to a second pole of the signal or supply voltage.

    摘要翻译: 载体包括:具有与第一接触孔的第一界面的基底和与第一界面相对的第二界面与第二接触孔。 基板包括基板主体和形成在其中的导电接触通道,其中每个接触通道将第一接触孔电连接到第二接触孔。 载体还包括布置在第一界面上的前侧布线层, 具有形成在其中的第一前侧金属化层,使得其包括用于将微电子器件和/或电路电连接到信号或电源电压的第一极的第一电容器电极。 至少部分地经由形成在载体中的电容器电介质的第一电容器电极电容耦合到第二前侧金属化层和/或衬底的导电区域,该区域至少部分地形成第二电容器电极,用于电连接微电子 设备和/或电路连接到信号或电源电压的第二极点。

    CHIP CARRIER WITH REDUCED INTERFERENCE SIGNAL SENSITIVITY
    10.
    发明申请
    CHIP CARRIER WITH REDUCED INTERFERENCE SIGNAL SENSITIVITY 有权
    具有降低干扰信号灵敏度的芯片载体

    公开(公告)号:US20070210417A1

    公开(公告)日:2007-09-13

    申请号:US11618172

    申请日:2006-12-29

    IPC分类号: H01L29/00

    摘要: Carrier including a substrate having a first interface with first contact holes, and a second interface, which lies opposite the first interface, with second contact holes. The substrate includes a substrate body and electrically conductive contact channels formed therein, wherein each of the contact channels electrically conductively connects a first contact hole to a second contact hole. The carrier also includes a front-side wiring layer arranged on the first interface and has a first front-side metallization layer formed therein such that it includes a first capacitor electrode for electrically connecting microelectronic devices and/or circuits to a first pole of a signal or supply voltage. The first capacitor electrode, at least partly via a capacitor dielectric formed in the carrier, couples capacitively to electrically conductive regions of a second front-side metallization layer and/or the substrate which at least partly form a second capacitor electrode for electrically connecting the microelectronic devices and/or circuits to a second pole of the signal or supply voltage.

    摘要翻译: 载体包括具有与第一接触孔的第一界面的基底和与第一界面相对的第二界面与第二接触孔。 基板包括基板主体和形成在其中的导电接触通道,其中每个接触通道将第一接触孔电连接到第二接触孔。 载体还包括布置在第一界面上并具有形成在其中的第一前侧金属化层的前侧布线层,使得其包括用于将微电子器件和/或电路电连接到信号的第一极的第一电容器电极 或电源电压。 至少部分地经由形成在载体中的电容器电介质的第一电容器电极电容耦合到第二前侧金属化层和/或衬底的导电区域,该区域至少部分地形成第二电容器电极,用于电连接微电子 设备和/或电路连接到信号或电源电压的第二极点。