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公开(公告)号：US4458406A
公开(公告)日：1984-07-10
申请号：US310337
申请日：1981-10-09
IPC分类号： H01L23/528 , H01L21/225 , H01L21/265 , H01L21/28
CPC分类号： H01L23/5286 , H01L2924/0002
摘要： The high resistance of diffused electrical interconnection lines used for ground return paths in MOS field effect transistor (MOSFET) arrays limits their size and performance. Advantage is taken of the extra interconnection level available from conventional double-layer-polycrystalline silicon (polysilicon) processes to distribute ground potential to arrays, by means of a polycrystalline grid with direct contact to diffused electrodes therein, thus greatly reducing the deleterious effects of ground resistance. The proposed ground grid is integrated into the structure of a MOSFET ROM using a typical double polysilicon process. The first polysilicon level provides the conductive medium for said ground grid and the diffusing doping impurities that form contiguous source electrodes for the array MOSFETs. Gate electrodes thereof and word lines are formed out of the second polysilicon level. Drain electrodes are diffused and contacted by metallized output lines.
摘要翻译： MOS场效应晶体管（MOSFET）阵列中用于接地回路的扩散电气互连线的高电阻限制了其尺寸和性能。 优点是可以利用传统的双层多晶硅（多晶硅）工艺提供的额外的互连级别，通过与其中的扩散电极直接接触的多晶网格将地电位分配到阵列，从而大大降低了地面的有害影响 抵抗性。 所提出的接地网格使用典型的双晶硅工艺集成到MOSFET ROM的结构中。 第一多晶硅层提供用于所述接地网格的导电介质和形成用于阵列MOSFET的连续源电极的扩散掺杂杂质。 其栅电极和字线由第二多晶硅层形成。 漏电极被金属化输出线扩散并接触。
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2.发明授权Phototransistor array having uniform current response and method of manufacture 失效具有均匀电流响应的光电晶体管阵列和制造方法
公开(公告)号：US4078243A
公开(公告)日：1978-03-07
申请号：US640376
申请日：1975-12-12
IPC分类号： H01L21/66 , H01L21/82 , H01L27/146 , H01L27/14
CPC分类号： H01L27/14692 , H01L21/82 , H01L27/14623 , H01L27/14681 , H01L22/14
摘要： Variations of current gain from element to element in a phototransistor array are eliminated by covering the array with an opaque mask and etching openings in the mask over each phototransistor based upon an area reduction factor (ARF). The area reduction factor for an opening is equal to (I.sub.m /I.sub.x).sup.1-n where n is a constant definitive of the change in beta of a phototransistor in the array over a given range of collector currents; I.sub.m is the minimum collector current measured for the array and I.sub.x is the collector current for the phototransistor beneath the opening. Based upon the ARF's, the openings etched in the mask or cover initiate uniform current from each phototransistor element when uniform light flux is directed on the array. The process of fabricating the array comprises measuring the collector current for each phototransistor element at a given uniform light flux; determining the element with minimum collector current in the array; calculating the ARF for each phototransistor to achieve a uniform current response from the array; coating the array with an opaque cover, and etching the cover at each phototransistor based upon the ARF.
摘要翻译： 基于面积减小因子（ARF），通过用不透明掩模覆盖阵列并在每个光电晶体管上的掩模中蚀刻开口来消除光电晶体管阵列中元件的电流增益的变化。 开口的面积缩小因子等于（Im / Ix）1-n，其中n是阵列中给定范围的集电极电流的光电晶体管的β的变化的常数定义; Im是针对阵列测量的最小集电极电流，Ix是开关下光电晶体管的集电极电流。 基于ARF，当均匀的光通量指向阵列时，蚀刻在掩模或盖中的开口引起来自每个光电晶体管元件的均匀电流。 制造阵列的过程包括在给定的均匀光通量下测量每个光电晶体管元件的集电极电流; 确定阵列中集电极电流最小的元件; 计算每个光电晶体管的ARF以实现阵列的均匀电流响应; 用不透明的盖子涂覆阵列，并且基于ARF在每个光电晶体管处蚀刻盖子。
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公开(公告)号：US4072868A
公开(公告)日：1978-02-07
申请号：US723678
申请日：1976-09-16
IPC分类号： H01L21/822 , H01L21/82 , H01L21/8238 , H01L27/04 , H01L27/088 , H01L27/092 , H01L29/78 , H03K17/687 , H03K19/094 , H03K19/0944 , H03K19/0948 , H03K19/08 , H01L27/08 , H03K19/40
CPC分类号： H01L27/092 , H01L21/82 , H01L27/0883 , H03K19/09482 , H01L27/0623
摘要： An insulated Gate Field Effect Transistor (IGFET) static inverter having an improved load line characteristic is disclosed. The inverter comprises an enhancement mode IGFET active device in a first portion of a semiconductor substrate, having its drain connected to an output node, its source connected to a source potential and its gate connected to an input signal source. The first portion of the substrate is connected to a first substrate potential. A depletion mode IGFET load device is located in a second portion of the semiconductor substrate which is electrically isolated from the first portion. The depletion mode load device has its drain connected to a drain potential and its source, gate and the second portion of the semiconductor substrate all connected to the output node. In this manner, the rise in the source-to-substrate voltage bias during the turn-off transition is eliminated in the depletion mode load device, providing an improved load current characteristic for the inverter. Alternate embodiments are disclosed directed to an all N-channel inverter, an all P-channel inverter, and a complementary inverter consisting of a P-channel load device and an N-channel active device.
摘要翻译： 公开了具有改进的负载线特性的绝缘栅场效应晶体管（IGFET）静态逆变器。 逆变器包括在半导体衬底的第一部分中的增强型IGFET有源器件，其漏极连接到输出节点，其源极连接到源极电势，并且其栅极连接到输入信号源。 衬底的第一部分连接到第一衬底电位。 耗尽型IGFET负载装置位于与第一部分电隔离的半导体衬底的第二部分中。 耗尽型负载装置的漏极连接到漏极电位，其源极，栅极和半导体衬底的第二部分都连接到输出节点。 以这种方式，在耗尽型负载装置中消除了关断转换期间的源至衬底电压偏压的上升，为逆变器提供了改进的负载电流特性。 公开了针对全N通道反相器，全P沟道反相器和由P沟道负载装置和N沟道有源装置组成的互补反相器的替代实施例。
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4.发明授权
公开(公告)号：US4280855A
公开(公告)日：1981-07-28
申请号：US114484
申请日：1980-01-23
CPC分类号： H01L29/78 , H01L21/2652 , H01L29/0847 , H01L29/1045
摘要： A diffused MOS (DMOS) device and method for making same are disclosed. The prior art DMOS device is improved upon by ion implanting a depletion extension L.sub.D to the drain. However, the introduction of the depletion extension L.sub.D introduces a manufacturing statistical variation in the characteristics of the resultant devices so produced. The problem of the effects of the variations in the length L.sub.D and thus, variations in the resulting transconductance of the device, is solved by placing two of these devices in parallel. When one device has its L.sub.D relatively shorter, the companion device will also have its L.sub.D correspondingly longer. The method of producing the dual devices is by ion implanting a single conductivity region which forms the L.sub.D for both the left- and right-hand channels for the left- and right-hand DMOS structures. If the mask for the ion-implanted region is misaligned slightly to the right, then the effective L.sub.D for the right-hand channel is somewhat longer but the effective L.sub.D for the left-hand channel is correspondingly shorter, so that the net parallel transconductance for the two devices remains the same as the transconductance for a perfectly symmetric ion-implanted region.
摘要翻译： 公开了扩散MOS（DMOS）器件及其制造方法。 通过将耗尽扩展LD离子注入到漏极来改进现有技术的DMOS器件。 然而，耗尽扩展LD的引入引入了如此制造的所得器件的特性的制造统计变化。 通过将这些器件中的两个并联放置，解决了长度LD + L的变化以及因此器件的所得跨导变化的影响的问题。 当一个设备的LD相对较短时，配套设备的LD相对较长。 制造双重器件的方法是通过离子注入形成用于左右DMOS结构的左通道和右通道的LD的单个导电区域。 如果离子注入区域的掩模略向右偏移，则右侧通道的有效LD稍长，但左侧通道的有效LD相应较短，因此， 两个器件保持与完全对称的离子注入区域的跨导相同。
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5.发明授权Method to fabricate ion-implanted layers with abrupt edges to reduce the parasitic resistance of Schottky barrier fets and bipolar transistors 失效制造具有突变边缘的离子注入层的方法，以降低肖特基势垒层和双极晶体管的寄生电阻
公开(公告)号：US4029522A
公开(公告)日：1977-06-14
申请号：US701375
申请日：1976-06-30
IPC分类号： H01L29/73 , H01L21/033 , H01L21/266 , H01L21/306 , H01L21/312 , H01L21/3205 , H01L21/331 , H01L21/338 , H01L21/74 , H01L23/52 , H01L29/732 , H01L29/80 , H01L29/812 , H01L21/265
CPC分类号： H01L29/7322 , H01L21/033 , H01L21/266 , H01L21/312 , H01L21/74 , H01L29/812 , Y10S438/951
摘要： A method is disclosed to implant layers in semiconductor substrates with asymmetrical edges, that is, one edge slopes towards the surface of the substrate and the other terminates abruptly inside the bulk. The method involves using lift-off techniques to make ion-stopping masks with near-vertical sidewalls which delineate the abrupt edges of the ion-implanted layers. The application of this method to fabricate Schottky barrier FET's and bipolar transistors yields devices with reduced parasitic resistance without adversely impacting other related electrical parameters such as breakdown voltage and capacitance.
摘要翻译： 公开了一种在具有不对称边缘的半导体衬底中注入层的方法，即，一个边缘朝向衬底的表面倾斜，而另一个边缘突然地在体内终止。 该方法涉及使用剥离技术来制造具有描绘离子注入层的突变边缘的近垂直侧壁的离子阻挡掩模。 该方法制造肖特基势垒FET和双极晶体管的应用产生具有降低的寄生电阻的器件，而不会不利地影响其他相关的电参数，例如击穿电压和电容。
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公开(公告)号：US4016587A
公开(公告)日：1977-04-05
申请号：US529193
申请日：1974-12-03
IPC分类号： H01L27/088 , H01L21/336 , H01L21/8234 , H01L23/532 , H01L29/08 , H01L29/78 , H01L29/06 , H01L29/04
CPC分类号： H01L29/66628 , H01L23/53271 , H01L29/0847 , H01L29/78 , H01L2924/0002 , Y10S257/90
摘要： Disclosed is an integrated circuit field effect transistor having a source and drain which protrude above the silicon substrate so as to create shallow junctions with the substrate while maintaining a relatively low sheet resistivity in the region. Two self-aligned source and drain fabrication processes are disclosed for the device. The first process yields a polysilicon field shield and the second process yields a field region composed of thermal silicon dioxide.
摘要翻译： 公开了一种集成电路场效应晶体管，其具有在硅衬底上方突出的源极和漏极，以便在该区域中保持相对低的片电阻率的同时与衬底形成浅结。 公开了用于该装置的两个自对准源极和漏极制造工艺。 第一种方法产生多晶硅场屏蔽，第二种方法产生由热二氧化硅组成的场区域。
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7.发明授权Charge pumping device with integrated regulating capacitor and method for making same 失效具有集成调节电容器的电荷泵装置及其制造方法
公开(公告)号：US4115794A
公开(公告)日：1978-09-19
申请号：US861311
申请日：1977-12-16
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H01L29/94 , H01L29/78
CPC分类号： H01L29/94 , H01L27/0222
摘要： An improved charge pumping device is disclosed for charge storage memory elements and substrate bias control. By selectively ion-implanting the substrate of the charge pump, its output current is substantially increased and its losses by charge dissipation are reduced. Charge pumps are used to charge a substrate-series capacitor combination to a desired bias point. In the substrate bias application, by integrating the series capacitor with the charge pump on the semiconductor chip and making the capacitor an integral part of a low resistance conductive blanket implant, the voltage regulation of the biasing circuit is improved.
摘要翻译： 公开了一种用于电荷存储存储元件和衬底偏置控制的改进的电荷泵送装置。 通过选择性地离子注入电荷泵的衬底，其输出电流显着增加，并且通过电荷耗散的损耗减小。 电荷泵用于将衬底串联电容器组合充电到所需的偏置点。 在衬底偏置应用中，通过将串联电容器与电荷泵集成在半导体芯片上并使电容器成为低电阻导电覆盖层注入的组成部分，改善了偏置电路的电压调节。
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8.发明授权Process for fabricating a low breakdown voltage device for polysilicon gate technology 失效用于制造多晶硅栅极技术的低击穿电压器件的工艺
公开(公告)号：US4102714A
公开(公告)日：1978-07-25
申请号：US679544
申请日：1976-04-23
IPC分类号： H01L29/78 , H01L21/20 , H01L21/306 , H01L27/02 , H01L29/06 , H01L29/866 , H01L21/22 , H01L21/302
CPC分类号： H01L21/02381 , H01L21/02532 , H01L21/02576 , H01L21/0262 , H01L21/30608 , H01L27/0255 , H01L29/0684 , Y10S148/168
摘要： A structure and process are disclosed for making a low-voltage breakdown p-n junction in a semiconductor substrate. The process comprises the step of etching a V-shaped groove in a semiconductor substrate of a first conductivity type, with an anistropic etchant, followed by depositing a layer of epitaxial semiconductor material of a second conductivity type in the V-shaped groove. There results a p-n junction with a small radius of curvature at the apex of the V-shaped groove having a correspondingly low breakdown voltage.
摘要翻译： 公开了用于在半导体衬底中制造低电压击穿p-n结的结构和工艺。 该方法包括用第一导电类型的半导体衬底中的V形槽蚀刻具有不平等蚀刻剂的步骤，然后在V形沟槽中沉积第二导电类型的外延半导体材料层。 在V形槽的顶点处形成具有小的曲率半径的p-n结，具有相应的低击穿电压。
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公开(公告)号：US4072545A
公开(公告)日：1978-02-07
申请号：US688811
申请日：1976-05-21
IPC分类号： H01L27/088 , H01L21/336 , H01L21/8234 , H01L23/532 , H01L29/08 , H01L29/78 , H01L21/265
CPC分类号： H01L29/66628 , H01L23/53271 , H01L29/0847 , H01L29/78 , H01L2924/0002 , Y10S257/90
摘要： Disclosed is an integrated circuit field effect transistor having a source and drain which protrude above the silicon substrate so as to create shallow junctions with the substrate while maintaining a relatively low sheet resistivity in the region. Two self-aligned source and drain fabrication processes are disclosed for the device. The first process yields a polysilicon field shield and the second process yields a field region composed of thermal silicon dioxide.
摘要翻译： 公开了一种集成电路场效应晶体管，其具有在硅衬底上方突出的源极和漏极，以便在该区域中保持相对较低的片电阻率的同时与衬底形成浅结。 公开了用于该装置的两个自对准源极和漏极制造工艺。 第一种方法产生多晶硅场屏蔽，第二种方法产生由热二氧化硅组成的场区域。
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10.发明授权
公开(公告)号：US4445267A
公开(公告)日：1984-05-01
申请号：US335953
申请日：1981-12-30
IPC分类号： H01L21/28 , H01L21/316 , H01L21/762 , H01L21/8234 , H01L21/8246 , H01L27/088 , H01L27/112 , H01L29/78 , H01L21/265
CPC分类号： H01L21/76216 , H01L21/28132 , H01L21/823456 , H01L27/088 , Y10S438/947
摘要： A method for fabricating a semiconductor integrated circuit structure having sub-micrometer gate length field effect transistor devices is described wherein a surface isolation pattern is formed in a semiconductor substrate which isolates regions of the semiconductor within the substrate from one another. Certain of these semiconductor regions are designated to contain field effect transistor devices. A first insulating layer such as silicon dioxide which is designated to be in part the gate dielectric layer of the field effect transistor devices is formed over the isolation pattern surface. Then a conductive layer, a second silicon dioxide layer, a first silicon nitride layer, a polycrystalline silicon layer and a second nitride layer are formed thereover. The multilayer structure is etched to result in a patterned polycrystalline silicon layer having substantially vertical sidewalls some of which sidewalls extend across certain of the device regions. A well controlled sub-micrometer thickness layer is formed on these vertical sidewalls by thermal oxidation of the polycrystalline silicon surfaces. The patterned layer is then removed which leaves the pattern of sub-micrometer thickness silicon dioxide sidewall layer portions of which extend across certain of the device regions. The sidewall layer is utilized as a mask in etching the first silicon nitride layer, the second silicon dioxide layer and the conductive layer to form the gate electrode of the field effect transistor devices in the conductive layer having the length of the sidewall coating. Ion implantation is then accomplished adjacent to the gate electrode to form the desired source/drain element for the field effect devices in the device regions. The conductive layer and resulting gate electrode may be composed of polycrystalline silicon metal silicide, polycide (a combination of layers of polycrystalline silicon and metal silicide) or the like.
摘要翻译： 描述了一种制造具有亚微米栅极长度场效应晶体管器件的半导体集成电路结构的方法，其中在半导体衬底中形成表面隔离图案，半导体衬底将衬底内的半导体区域彼此隔离。 这些半导体区域中的某些被指定为包含场效应晶体管器件。 在隔离图案表面上形成第一绝缘层，例如被指定为场效应晶体管器件的栅介电层的一部分的二氧化硅。 然后在其上形成导电层，第二二氧化硅层，第一氮化硅层，多晶硅层和第二氮化物层。 蚀刻多层结构以产生具有基本垂直侧壁的图案化多晶硅层，其中一些侧壁延伸穿过特定的器件区域。 通过多晶硅表面的热氧化，在这些垂直侧壁上形成良好控制的亚微米厚度层。 然后去除图案层，其留下亚微米厚度的二氧化硅侧壁层的图案，其部分延伸穿过特定的器件区域。 在蚀刻第一氮化硅层，第二二氧化硅层和导电层时，将侧壁层用作掩模，以在具有侧壁涂层长度的导电层中形成场效应晶体管器件的栅电极。 然后在栅电极附近实现离子注入，以形成用于器件区域中的场效应器件的所需源极/漏极元件。 导电层和所得到的栅电极可以由多晶硅金属硅化物，多晶硅（多晶硅和金属硅化物的组合）等构成。
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