公开(公告)号：US08240027B2

公开(公告)日：2012-08-14

申请号：US12007820

申请日：2008-01-16

申请人： Frank D. Egitto ,  John S. Kresge ,  John M. Lauffer

发明人： Frank D. Egitto ,  John S. Kresge ,  John M. Lauffer

IPC分类号： H01C17/06 ,  H01C17/24 ,  H01C17/242

CPC分类号： H01C17/06 ,  H01C17/24 ,  H05K1/0268 ,  H05K1/167 ,  H05K2201/0355 ,  H05K2201/0969 ,  H05K2203/0361 ,  H05K2203/171 ,  Y10T29/49099 ,  Y10T29/49101

摘要： A method of making a circuitized substrate which involves forming a plurality of individual film resistors having approximate resistance values as part of at least one circuit of the substrate, measuring the resistance of a representative (sample) resistor to define its resistance, utilizing these measurements to determine the corresponding precise width of other, remaining film resistors located in a defined proximity relative to the representative resistor such that these remaining film resistors will include a defined resistance value, and then selectively isolating defined portions of the resistive material of these remaining film resistors while simultaneously defining the precise width of the resistive material in order that these film resistors will possess the defined resistance.

摘要翻译： 一种制造电路化衬底的方法，其包括形成具有近似电阻值的多个单独的膜电阻器作为衬底的至少一个电路的一部分，测量代表性（样品）电阻器的电阻以限定其电阻，利用这些测量 确定位于相对于代表性电阻器确定的接近度的其它剩余膜电阻器的对应精确宽度，使得这些剩余的膜电阻器将包括限定的电阻值，然后选择性地隔离这些剩余膜电阻器的电阻材料的限定部分，同时 同时限定电阻材料的精确宽度，以使这些薄膜电阻器具有限定的电阻。

公开(公告)号：US20090178271A1

公开(公告)日：2009-07-16

申请号：US12007820

申请日：2008-01-16

申请人： Frank D. Egitto ,  John S. Kresge ,  John M. Lauffer

发明人： Frank D. Egitto ,  John S. Kresge ,  John M. Lauffer

IPC分类号： H01C17/06

CPC分类号： H01C17/06 ,  H01C17/24 ,  H05K1/0268 ,  H05K1/167 ,  H05K2201/0355 ,  H05K2201/0969 ,  H05K2203/0361 ,  H05K2203/171 ,  Y10T29/49099 ,  Y10T29/49101

摘要： A method of making a circuitized substrate which involves forming a plurality of individual film resistors having approximate resistance values as part of at least one circuit of the substrate, measuring the resistance of a representative (sample) resistor to define its resistance, utilizing these measurements to determine the corresponding precise width of other, remaining film resistors located in a defined proximity relative to the representative resistor such that these remaining film resistors will include a defined resistance value, and then selectively isolating defined portions of the resistive material of these remaining film resistors while simultaneously defining the precise width of the resistive material in order that these film resistors will possess the defined resistance.

摘要翻译： 一种制造电路化衬底的方法，其包括形成具有近似电阻值的多个单独的膜电阻器作为衬底的至少一个电路的一部分，测量代表性（样品）电阻器的电阻以限定其电阻，利用这些测量 确定位于相对于代表性电阻器确定的接近度的其它剩余膜电阻器的对应精确宽度，使得这些剩余的膜电阻器将包括限定的电阻值，然后选择性地隔离这些剩余膜电阻器的电阻材料的限定部分，同时 同时限定电阻材料的精确宽度，以使这些薄膜电阻器具有限定的电阻。

公开(公告)号：US08607445B1

公开(公告)日：2013-12-17

申请号：US13517776

申请日：2012-06-14

申请人： Rabindra N. Das ,  Frank D. Egitto ,  John M. Lauffer ,  How T. Lin

发明人： Rabindra N. Das ,  Frank D. Egitto ,  John M. Lauffer ,  How T. Lin

IPC分类号： H05K3/30

CPC分类号： H01G4/206 ,  H01G4/232 ,  H01G4/33 ,  H05K1/162 ,  H05K3/0032 ,  H05K3/107 ,  H05K2201/0209 ,  H05K2201/0257 ,  H05K2201/09236 ,  H05K2201/09309 ,  H05K2201/09881 ,  H05K2203/0108 ,  H05K2203/066

摘要： A method of making a circuitized substrate which includes at least one and possibly several capacitors as part thereof. In one embodiment, the substrate is produced by forming a layer of capacitive dielectric material on a dielectric layer and thereafter forming channels with the capacitive material, e.g., using a laser. The channels are then filled with conductive material, e.g., copper, using selected deposition techniques, e.g., sputtering, electro-less plating and electroplating. A second dielectric layer is then formed atop the capacitor and a capacitor “core” results. This “core” may then be combined with other dielectric and conductive layers to form a larger, multilayered PCB or chip carrier. In an alternative approach, the capacitive dielectric material may be photo-imageable, with the channels being formed using conventional exposure and development processing known in the art.

摘要翻译： 一种制造电路化衬底的方法，其包括至少一个可能的几个电容器作为其一部分。 在一个实施例中，通过在电介质层上形成电容电介质材料层，然后用电容材料形成通道，例如使用激光来制造衬底。 然后使用所选择的沉积技术，例如溅射，无电镀和电镀，用导电材料（例如铜）填充通道。 然后在电容器顶部形成第二电介质层，并产生电容器“芯”。 然后，该“芯”可以与其它电介质层和导电层组合以形成较大的多层PCB或芯片载体。 在替代方法中，电容介电材料可以是可光成像的，其中通道是使用本领域已知的常规曝光和显影处理形成的。

公开(公告)号：US07897877B2

公开(公告)日：2011-03-01

申请号：US11438424

申请日：2006-05-23

申请人： Rabindra N. Das ,  Frank D. Egitto ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich

发明人： Rabindra N. Das ,  Frank D. Egitto ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich

IPC分类号： H05K1/16

CPC分类号： H05K1/162 ,  H01L27/12 ,  H01L28/40 ,  H05K1/0306 ,  H05K3/125 ,  H05K3/4667 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2203/013

摘要： A capacitive substrate and method of making same in which first and second glass layers are used. A first conductor is formed on a first of the glass layers and a capacitive dielectric material is positioned over the conductor. The second conductor is then positioned on the capacitive dielectric and the second glass layer positioned over the second conductor. Conductive thru-holes are formed to couple to the first and second conductors, respectively, such that the conductors and capacitive dielectric material form a capacitor when the capacitive substrate is in operation.

摘要翻译： 电容性基板及其制造方法，其中使用第一和第二玻璃层。 第一导体形成在第一玻璃层上，并且电容电介质材料位于导体上方。 然后将第二导体定位在电容电介质上，并且第二玻璃层位于第二导体上。 形成导电通孔以分别耦合到第一和第二导体，使得当电容基板工作时，导体和电容电介质材料形成电容器。

公开(公告)号：US07307022B2

公开(公告)日：2007-12-11

申请号：US11327493

申请日：2006-01-09

申请人： Frank D. Egitto ,  Stephen Krasniak ,  John M. Lauffer ,  Voya R. Markovich ,  Luis J. Matienzo

发明人： Frank D. Egitto ,  Stephen Krasniak ,  John M. Lauffer ,  Voya R. Markovich ,  Luis J. Matienzo

IPC分类号： H01L21/44 ,  C25D5/02

CPC分类号： H05K3/384 ,  H05K1/056 ,  H05K3/386 ,  H05K2201/0355 ,  H05K2201/0358 ,  H05K2203/0353 ,  H05K2203/0723

摘要： A method of treating a conductive layer to assure enhanced adhesion of the layer to selected dielectric layers used to form a circuitized substrate. The conductive layer includes at least one surface with the appropriate roughness to enable such adhesion and also good signal passage if the layer is used as a signal layer. The method is extendible to the formation of such substrates, including to the formation of multilayered substrates having many conductive and dielectric layers. Such substrates may include one or more electrical components (e.g., semiconductor chips) mounted thereon and may also be mounted themselves onto other substrates.

摘要翻译： 一种处理导电层以确保该层对用于形成电路化基底的所选电介质层的附着力的方法。 导电层包括具有适当粗糙度的至少一个表面以实现这种粘附，并且如果该层用作信号层，则还具有良好的信号通过。 该方法可扩展到形成这种衬底，包括形成具有许多导电和电介质层的多层衬底。 这样的基板可以包括安装在其上的一个或多个电气部件（例如，半导体芯片），并且也可以将它们本身安装到其它基板上。

公开(公告)号：US07800916B2

公开(公告)日：2010-09-21

申请号：US11783306

申请日：2007-04-09

申请人： Kim J. Blackwell ,  Frank D. Egitto ,  John M. Lauffer ,  Voya R. Markovich

发明人： Kim J. Blackwell ,  Frank D. Egitto ,  John M. Lauffer ,  Voya R. Markovich

IPC分类号： H01R12/16

CPC分类号： H05K1/186 ,  H01L23/4985 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K3/4611 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/10515 ,  H05K2201/10681 ,  Y10T29/49126 ,  Y10T29/49151 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/0401

摘要： A circuitized substrate assembly comprised of at least two circuitized substrates each including a thin dielectric layer and a conductive layer with a plurality of conductive members as part thereof, the conductive members of each substrate being electrically coupled to the conductive sites of a semiconductor chip. A dielectric layer is positioned between both substrates and the substrates are bonded together, such that the chips are internally located within the assembly and oriented in a stacked orientation. A method of making such an assembly is also provided, as is an electrical assembly utilizing same and an information handling system adapted for having such an electrical assembly as part thereof.

摘要翻译： 电路化衬底组件由至少两个电路化衬底组成，每个衬底均包括薄介电层和具有多个导电构件作为其一部分的导电层，每个衬底的导电构件电耦合到半导体芯片的导电部位。 电介质层位于两个基板之间，并且基板接合在一起，使得芯片在内部位于组件内并且以堆叠取向定向。 还提供了制造这种组件的方法，以及使用其的电组件以及适于将这种电组件作为其一部分的信息处理系统。

公开(公告)号：US20070275525A1

公开(公告)日：2007-11-29

申请号：US11438424

申请日：2006-05-23

申请人： Rabindra N. Das ,  Frank D. Egitto ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich

发明人： Rabindra N. Das ,  Frank D. Egitto ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich

IPC分类号： H01L21/8242

CPC分类号： H05K1/162 ,  H01L27/12 ,  H01L28/40 ,  H05K1/0306 ,  H05K3/125 ,  H05K3/4667 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2203/013

摘要： A capacitive substrate and method of making same in which first and second glass layers are used. A first conductor is formed on a first of the glass layers and a capacitive dielectric material is positioned over the conductor. The second conductor is then positioned on the capacitive dielectric and the second glass layer positioned over the second conductor. Conductive thru-holes are formed to couple to the first and second conductors, respectively, such that the conductors and capacitive dielectric material form a capacitor when the capacitive substrate is in operation.

摘要翻译： 电容性基板及其制造方法，其中使用第一和第二玻璃层。 第一导体形成在第一玻璃层上，并且电容电介质材料位于导体上方。 然后将第二导体定位在电容电介质上，并且第二玻璃层位于第二导体上。 形成导电通孔以分别耦合到第一和第二导体，使得当电容基板工作时，导体和电容电介质材料形成电容器。

公开(公告)号：US08501575B2

公开(公告)日：2013-08-06

申请号：US12909983

申请日：2010-10-22

申请人： Rabindra N. Das ,  Frank D. Egitto ,  How T. Lin ,  John M. Lauffer ,  Voya R. Markovich

发明人： Rabindra N. Das ,  Frank D. Egitto ,  How T. Lin ,  John M. Lauffer ,  Voya R. Markovich

IPC分类号： H01G4/00

CPC分类号： H01G4/206 ,  H01G4/232 ,  H01G4/33 ,  H05K1/162 ,  H05K3/06 ,  H05K3/125 ,  H05K3/18 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/0257 ,  H05K2201/09309 ,  Y10T156/10

摘要： Methods of forming embedded, multilayer capacitors in printed circuit boards wherein copper or other electrically conductive channels are formed on a dielectric substrate. The channels may be preformed using etching or deposition techniques. A photoimageable dielectric is an upper surface of the laminate. Exposing and etching the photoimageable dielectric exposes the space between the copper traces. These spaces are then filled with a capacitor material. Finally, copper is either laminated or deposited atop the structure. This upper copper layer is then etched to provide electrical interconnections to the capacitor elements. Traces may be formed to a height to meet a plane defining the upper surface of the dielectric substrate or thin traces may be formed on the remaining dielectric surface and a secondary copper plating process is utilized to raise the height of the traces.

摘要翻译： 在印刷电路板中形成嵌入式多层电容器的方法，其中在电介质基板上形成铜或其它导电通道。 通道可以使用蚀刻或沉积技术进行。 可光成像的电介质是层叠体的上表面。 曝光和蚀刻可光成像电介质暴露铜迹线之间的空间。 然后用电容器材料填充这些空间。 最后，铜层压或沉积在结构的顶部。 然后对该上铜层进行蚀刻，以提供与电容器元件的电互连。 迹线可以形成为高度以满足限定电介质基板的上表面的平面，或者可以在剩余的电介质表面上形成薄迹线，并且使用二次镀铜工艺来提高迹线的高度。

公开(公告)号：US20120223047A1

公开(公告)日：2012-09-06

申请号：US12909983

申请日：2010-10-22

申请人： Rabindra N. Das ,  Frank D. Egitto ,  How T. Lin ,  John M. Lauffer ,  Voya R. Markovich

发明人： Rabindra N. Das ,  Frank D. Egitto ,  How T. Lin ,  John M. Lauffer ,  Voya R. Markovich

IPC分类号： H01G4/002 ,  G03F7/30 ,  G03F7/20

CPC分类号： H01G4/206 ,  H01G4/232 ,  H01G4/33 ,  H05K1/162 ,  H05K3/06 ,  H05K3/125 ,  H05K3/18 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/0257 ,  H05K2201/09309 ,  Y10T156/10

摘要： Methods of forming embedded, multilayer capacitors in printed circuit boards wherein copper or other electrically conductive channels are formed on a dielectric substrate. The channels may be preformed using etching or deposition techniques. A photoimageable dielectric is an upper surface of the laminate. Exposing and etching the photoimageable dielectric exposes the space between the copper traces. These spaces are then filled with a capacitor material. Finally, copper is either laminated or deposited atop the structure. This upper copper layer is then etched to provide electrical interconnections to the capacitor elements. Traces may be formed to a height to meet a plane defining the upper surface of the dielectric substrate or thin traces may be formed on the remaining dielectric surface and a secondary copper plating process is utilized to raise the height of the traces.

摘要翻译： 在印刷电路板中形成嵌入式多层电容器的方法，其中在电介质基板上形成铜或其它导电通道。 通道可以使用蚀刻或沉积技术进行。 可光成像的电介质是层叠体的上表面。 曝光和蚀刻可光成像电介质暴露铜迹线之间的空间。 然后用电容器材料填充这些空间。 最后，铜层压或沉积在结构的顶部。 然后对该上铜层进行蚀刻，以提供与电容器元件的电互连。 迹线可以形成为高度以满足限定电介质基板的上表面的平面，或者可以在剩余的电介质表面上形成薄迹线，并且使用二次镀铜工艺来提高迹线的高度。

公开(公告)号：US20080248596A1

公开(公告)日：2008-10-09

申请号：US11878673

申请日：2007-07-26

申请人： Rabindra N. Das ,  Frank D. Egitto ,  How T. Lin ,  John M. Lauffer ,  Voya R. Markovich

发明人： Rabindra N. Das ,  Frank D. Egitto ,  How T. Lin ,  John M. Lauffer ,  Voya R. Markovich

IPC分类号： H01L21/77

CPC分类号： H01G4/206 ,  H01G4/232 ,  H01G4/33 ,  H05K1/162 ,  H05K3/0032 ,  H05K3/107 ,  H05K2201/0209 ,  H05K2201/0257 ,  H05K2201/09236 ,  H05K2201/09309 ,  H05K2201/09881 ,  H05K2203/0108 ,  H05K2203/066

摘要： A method of making a circuitized substrate which includes at least one and possibly several capacitors as part thereof. In one embodiment, the substrate is produced by forming a layer of capacitive dielectric material on a dielectric layer and thereafter forming channels with the capacitive material, e.g., using a laser. The channels are then filled with conductive material, e.g., copper, using selected deposition techniques, e.g., sputtering, electro-less plating and electroplating. A second dielectric layer is then formed atop the capacitor and a capacitor “core” results. This “core” may then be combined with other dielectric and conductive layers to form a larger, multilayered PCB or chip carrier. In an alternative approach, the capacitive dielectric material may be photo-imageable, with the channels being formed using conventional exposure and development processing known in the art. In still another embodiment, at least two spaced-apart conductors may be formed within a metal layer deposited on a dielectric layer, these conductors defining a channel there-between. The capacitive dielectric material may then be deposited (e.g., using lamination) within the channels.

摘要翻译： 一种制造电路化衬底的方法，其包括至少一个可能的几个电容器作为其一部分。 在一个实施例中，通过在电介质层上形成电容电介质材料层，然后用电容材料形成通道，例如使用激光来制造衬底。 然后使用所选择的沉积技术，例如溅射，无电镀和电镀，用导电材料（例如铜）填充通道。 然后在电容器顶部形成第二电介质层，并产生电容器“芯”。 然后，该“芯”可以与其它电介质层和导电层组合以形成较大的多层PCB或芯片载体。 在替代方法中，电容介电材料可以是可光成像的，其中通道是使用本领域已知的常规曝光和显影处理形成的。 在另一个实施例中，可以在沉积在电介质层上的金属层内形成至少两个间隔开的导体，这些导体在其间限定通道。 然后可以在通道内沉积（例如，使用层压）的电容电介质材料。