公开(公告)号：US20050283335A1

公开(公告)日：2005-12-22

申请号：US11160086

申请日：2005-06-08

申请人： G. Banke ,  Andrew Deering ,  Philip Kaszuba ,  Leon Moszkowicz ,  James Robert ,  James Slinkman

发明人： G. Banke ,  Andrew Deering ,  Philip Kaszuba ,  Leon Moszkowicz ,  James Robert ,  James Slinkman

IPC分类号： A61M1/00 ,  G01N1/32 ,  G01Q30/04 ,  G01Q30/20 ,  G01Q60/00 ,  G01R31/28 ,  G06F19/00 ,  H01L21/66

CPC分类号： A61M1/0058 ,  A61M1/0084 ,  G01N1/32 ,  G01R31/2898

摘要： A method for measuring an integrated circuit (IC) structure by measuring an imprint of the structure, a method for preparing a test site for the above measuring, and IC so formed. The method for preparing the test site includes incrementally removing the structure from the substrate so as to reveal an imprint of the removed bottom surface of the structure in a top surface of the substrate. The imprint can then be imaged using an atomic force microscope (AFM). The image can be used to measure the bottom surface of the structure.

摘要翻译： 通过测量结构的印记来测量集成电路（IC）结构的方法，制备用于上述测量的测试部位的方法和如此形成的IC。 用于制备测试部位的方法包括从衬底逐渐去除结构，以便在衬底的顶表面中露出结构的去除的底表面的印记。 然后可以使用原子力显微镜（AFM）对印记进行成像。 该图像可用于测量结构的底面。

公开(公告)号：US20080050931A1

公开(公告)日：2008-02-28

申请号：US11926613

申请日：2007-10-29

申请人： Toshiharu Furukawa ,  Charles Koburger ,  James Slinkman

发明人： Toshiharu Furukawa ,  Charles Koburger ,  James Slinkman

IPC分类号： H01L21/31

CPC分类号： H01L21/7624 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78645 ,  H01L29/78654

摘要： A silicon-on-insulator (SOI) device and structure having locally strained regions in the silicon active layer formed by increasing the thickness of underlying regions of a buried insulating layer separating the silicon active layer from the substrate. The stress transferred from the underlying thickened regions of the insulating layer to the overlying strained regions increases carrier mobility in these confined regions of the active layer. Devices formed in and on the silicon active layer may benefit from the increased carrier mobility in the spaced-apart strained regions.

摘要翻译： 通过增加将硅有源层与衬底分离的掩埋绝缘层的下面的区域的厚度形成在硅有源层中具有局部应变区的绝缘体上硅（SOI）器件和结构。 从绝缘层的下面的加厚区域转移到上覆的应变区域的应力增加了活性层的这些受限区域中的载流子迁移率。 在有源层中形成的器件可以受益于间隔开的应变区域中增加的载流子迁移率。

公开(公告)号：US20070170515A1

公开(公告)日：2007-07-26

申请号：US11275644

申请日：2006-01-20

申请人： David Collins ,  James Slinkman ,  Steven Voldman

发明人： David Collins ,  James Slinkman ,  Steven Voldman

IPC分类号： H01L29/76 ,  H01L21/8238

CPC分类号： H01L27/0928 ,  H01L21/761 ,  H01L27/0921 ,  H01L29/1087

摘要： Disclosed is a triple well CMOS device structure that addresses the issue of latchup by adding an n+ buried layer not only beneath the p-well to isolate the p-well from the p− substrate but also beneath the n-well. The structure eliminates the spacing issues between the n-well and n+ buried layer by extending the n+ buried layer below the entire device. The structure also addresses the issue of threshold voltage scattering by providing a p+ buried layer below the entire device under the n+ buried layer or below the p-well side of the device only either under or above the n+ buried layer) Latchup robustness can further be improved by incorporating into the device an isolation structure that eliminates lateral pnp, npn, or pnpn devices and/or a sub-collector region between the n+ buried layer and the n-well.

摘要翻译： 公开了一种三阱CMOS器件结构，其通过在p阱下面添加n +掩埋层来解决闭锁的问题，以将p阱与p-衬底隔离，但也在n阱下方。 该结构通过将n +掩埋层延伸到整个器件的下方来消除n阱和n +掩埋层之间的间隔问题。 该结构还通过在n +掩埋层下方的整个器件下方或仅在器件的p阱侧下面的p +掩埋层提供阈值电压散射的问题，仅在n +掩埋层之下或之上）锁存稳健性可以进一步 通过将在n +掩埋层和n阱之间消除侧向pnp，npn或pnpn器件和/或子集电极区域的隔离结构结合到器件中来改进。

公开(公告)号：US20060060562A1

公开(公告)日：2006-03-23

申请号：US10711458

申请日：2004-09-20

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit ,  James Slinkman

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit ,  James Slinkman

IPC分类号： C23F1/00 ,  B44C1/22 ,  G03C5/00

CPC分类号： H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139

摘要： A method of patterning which provides images substantially smaller than that possible by lithographic techniques is provided. In the method of the invention, a substrate has a memory layer and a sacrificial layer formed thereon. An image is patterned onto the memory layer by protecting an edge during an etching step using chemical oxide removal (COR) processes, for example. Another edge is memorized in the layer. The sacrificial layer is removed to expose another memorized edge, which is used to define a pattern in an underlying layer.

摘要翻译： 提供了一种通过光刻技术提供显着小于可能的图像的图案化方法。 在本发明的方法中，衬底具有形成在其上的存储层和牺牲层。 例如，通过使用化学氧化物去除（COR）工艺在蚀刻步骤期间保护边缘，将图像图案化到存储层上。 另一个边缘被记住在图层中。 去除牺牲层以露出另一个存储的边缘，其用于在下层中定义图案。

公开(公告)号：US20070099386A1

公开(公告)日：2007-05-03

申请号：US11163791

申请日：2005-10-31

申请人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Robert Rassel ,  James Slinkman ,  Michael Zierak

发明人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Robert Rassel ,  James Slinkman ,  Michael Zierak

IPC分类号： H01L21/336 ,  H01L29/788

CPC分类号： H01L29/66659 ,  H01L21/26586

摘要： A method for fabricating high gain FETs that substantially reduces or eliminates unwanted variation in device characteristics caused by using a prior art shadow masking process is provided. The inventive method employs a blocking mask that at least partially extends over the gate region wherein after extension and halo implants an FET having an asymmetric halo region asymmetric extension regions or a combination thereof is fabricated. The inventive method thus provides high gain FETs in which the variation of device characteristics is substantially reduced. The present invention also relates to the resulting asymmetric high gain FET device that is fabricated utilizing the method of the present invention.

摘要翻译： 提供了一种制造高增益FET的方法，其基本上减少或消除了由使用现有技术的阴影掩蔽处理引起的器件特性的不必要的变化。 本发明的方法采用阻挡掩模，其在栅极区域上至少部分地延伸，其中在延伸和卤素注入之后，制造具有不对称卤素区域不对称延伸区域或其组合的FET。 因此，本发明的方法提供了高增益FET，其中器件特性的变化显着降低。 本发明还涉及利用本发明的方法制造的非对称高增益FET器件。

公开(公告)号：US20060195285A1

公开(公告)日：2006-08-31

申请号：US10906590

申请日：2005-02-25

申请人： Pierre Bouchard ,  Mark Hakey ,  Mark Masters ,  Leah Pastel ,  James Slinkman ,  David Vallett

发明人： Pierre Bouchard ,  Mark Hakey ,  Mark Masters ,  Leah Pastel ,  James Slinkman ,  David Vallett

IPC分类号： G06F19/00

CPC分类号： G01R31/2856 ,  G01R31/2831 ,  G01R31/318511 ,  G01R31/3187

摘要： A diagnostic system and method for testing an integrated circuit (IC) during fabrication thereof, wherein the diagnostic system comprises at least one IC chip comprising an electrical signature; a sacrificial circuit adjacent to the IC chip and comprising a known electrical signature and intentionally mis-designed circuitry; and a comparator adapted to compare the electrical signature of the IC chip with the known electrical signature of the sacrificial circuit, wherein a match in the electrical signature of the IC chip with the known electrical signature of the sacrificial circuit indicates that the IC chip is mis-designed. The diagnostic system further comprises a semiconductor wafer comprising a plurality of IC chips and a kerf area separating one IC chip from another IC chip. The sacrificial circuit is located in the kerf area or alternatively on each of the plurality of IC chips. A mis-designed IC chip comprises abnormally functioning circuitry.

摘要翻译： 一种用于在其制造期间测试集成电路（IC）的诊断系统和方法，其中所述诊断系统包括至少一个包括电特征的IC芯片; 邻近于IC芯片的牺牲电路，包括已知的电气签名和故意错误设计的电路; 以及比较器，用于将IC芯片的电气签名与牺牲电路的已知电气签名进行比较，其中IC芯片的电子签名与牺牲电路的已知电气签名的匹配表明IC芯片是错误的 设计。 诊断系统还包括半导体晶片，其包括多个IC芯片和将IC芯片与另一IC芯片分开的切口区域。 牺牲电路位于切口区域中，或者替代地位于多个IC芯片中的每一个上。 错误设计的IC芯片包括异常功能的电路。

公开(公告)号：US20060146313A1

公开(公告)日：2006-07-06

申请号：US10905453

申请日：2005-01-05

申请人： Emily Gallagher ,  Louis Kindt ,  James Slinkman ,  Richard Wistrom

发明人： Emily Gallagher ,  Louis Kindt ,  James Slinkman ,  Richard Wistrom

IPC分类号： G03B27/62

CPC分类号： G03F1/64 ,  G03F1/60

摘要： A method for adjusting the flatness of a lithographic mask includes determining an initial mask flatness of the mask, determining an applied stress for bringing the mask to a desired mask flatness, and determining a mounting temperature of a pellicle frame to be mounted to the mask, the mounting temperature corresponding to the applied stress. The actual temperature of the pellicle frame is adjusted to the determined mounting temperature.

摘要翻译： 调整光刻掩模的平坦度的方法包括：确定掩模的初始掩模平坦度，确定施加的应力以使掩模达到期望的掩模平坦度，以及确定要安装到掩模的防护薄膜组件框架的安装温度， 安装温度对应于施加的应力。 将防护膜框架的实际温度调整到确定的安装温度。

公开(公告)号：US20050227498A1

公开(公告)日：2005-10-13

申请号：US10814482

申请日：2004-03-31

申请人： Toshiharu Furukawa ,  Charles Koburger ,  James Slinkman

发明人： Toshiharu Furukawa ,  Charles Koburger ,  James Slinkman

IPC分类号： H01L21/336 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L21/469

CPC分类号： H01L21/7624 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78645 ,  H01L29/78654

摘要： A silicon-on-insulator (SOI) device and structure having locally strained regions in the silicon active layer formed by increasing the thickness of underlying regions of a buried insulating layer separating the silicon active layer from the substrate. The stress transferred from the underlying thickened regions of the insulating layer to the overlying strained regions increases carrier mobility in these confined regions of the active layer. Devices formed in and on the silicon active layer may benefit from the increased carrier mobility in the spaced-apart strained regions.

摘要翻译： 通过增加将硅有源层与衬底分离的掩埋绝缘层的下面的区域的厚度形成在硅有源层中具有局部应变区的绝缘体上硅（SOI）器件和结构。 从绝缘层的下面的加厚区域转移到上覆的应变区域的应力增加了活性层的这些受限区域中的载流子迁移率。 在有源层中形成的器件可以受益于间隔开的应变区域中增加的载流子迁移率。

公开(公告)号：US20050087875A1

公开(公告)日：2005-04-28

申请号：US10605766

申请日：2003-10-24

申请人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit ,  James Slinkman

发明人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit ,  James Slinkman

IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L29/40

CPC分类号： H01L21/7682 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a gas dielectric with support structure on a semiconductor device structure provides low capacitance and adequate support for a conductor of the semiconductor device structure. A conductive structure, such as via or interconnect, is formed in a wiring-layer dielectric. A support is then formed that connects to the conductive structure, the support including an area thereunder. The wiring-layer dielectric is then removed from the area to form a gas dielectric.

摘要翻译： 在半导体器件结构上形成具有支撑结构的气体电介质的方法为半导体器件结构的导体提供低电容和足够的支撑。 在布线层电介质中形成诸如通孔或互连的导电结构。 然后形成连接到导电结构的支撑件，支撑件包括其下的区域。 然后从该区域去除布线层电介质以形成气体电介质。

公开(公告)号：US08227318B2

公开(公告)日：2012-07-24

申请号：US12622028

申请日：2009-11-19

申请人： Max Levy ,  Natalie Feilchenfeld ,  Richard Phelps ,  BethAnn Rainey ,  James Slinkman ,  Steven H. Voldman ,  Michael Zierak ,  Hubert Enichlmair ,  Martin Knaipp ,  Bernard Loeffler ,  Rainer Minixhofer ,  Jong-Mun Park ,  Georg Roehrer

发明人： Max Levy ,  Natalie Feilchenfeld ,  Richard Phelps ,  BethAnn Rainey ,  James Slinkman ,  Steven H. Voldman ,  Michael Zierak ,  Hubert Enichlmair ,  Martin Knaipp ,  Bernard Loeffler ,  Rainer Minixhofer ,  Jong-Mun Park ,  Georg Roehrer

IPC分类号： H01L21/762

CPC分类号： H01L21/76232 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/31111 ,  H01L21/76229

摘要： A method of forming an isolation region is provided that in one embodiment substantially reduces divot formation. In one embodiment, the method includes providing a semiconductor substrate, forming a first pad dielectric layer on an upper surface of the semiconductor substrate and forming a trench through the first pad dielectric layer into the semiconductor substrate. In a following process sequence, the first pad dielectric layer is laterally etched to expose an upper surface of the semiconductor substrate that is adjacent the trench, and the trench is filled with a trench dielectric material, wherein the trench dielectric material extends atop the upper surface of the semiconductor substrate adjacent the trench and abuts the pad dielectric layer.

摘要翻译： 提供了一种形成隔离区域的方法，其在一个实施方案中基本上减少了凹陷形成。 在一个实施例中，该方法包括提供半导体衬底，在半导体衬底的上表面上形成第一焊盘电介质层，并通过第一焊盘电介质层形成通向半导体衬底的沟槽。 在下面的处理顺序中，第一焊盘介电层被横向蚀刻以暴露与沟槽相邻的半导体衬底的上表面，并且沟槽填充有沟槽电介质材料，其中沟槽电介质材料在上表面 所述半导体衬底与所述沟槽相邻并且邻接所述焊盘介电层。