公开(公告)号：US3906544A

公开(公告)日：1975-09-16

申请号：US46292474

申请日：1974-04-22

Applicant: GEN ELECTRIC

Inventor： ENGELER WILLIAM E ,  TIEMANN JEROME J

IPC: H01L27/108 ,  H01L27/148 ,  H01L11/14

CPC classification number: H01L27/108 ,  H01L27/14831

Abstract: A radiation responsive semiconductor imaging device comprising an array of charge storage devices arranged in rows and columns on the surface of a semiconductor substrate. Each storage device includes a conductor-insulator-semiconductor structure in which minority carriers, controllably generated within the semiconductor in proportional response to incident electromagnetic radiation flux, are stored at the surface of the semiconductor beneath the conductor due to the application of a depletion region forming voltage to the conductor. Means are disclosed for transferring the integrated electrical charge from the storage region to a receiver region for electrical readout of the stored information. Means for reading out selected electrical charges while continuing to store other electrical charges are also disclosed. Means are also disclosed for altering the sensitivity of the array without a sacrifice in dynamic range.

Abstract translation: 一种辐射响应半导体成像装置，包括在半导体衬底的表面上以行和列布置的电荷存储装置的阵列。 每个存储装置包括导体 - 绝缘体 - 半导体结构，其中由半导体中可控地产生的少数载流子与入射电磁辐射通量成正比地存储在导体下方的半导体表面处，这是由于施加耗尽区形成 导体电压。 公开了用于将积分电荷从存储区域传送到接收器区域以便电存储信息的装置。 还公开了在继续存储其他电荷的同时读取所选择的电荷的装置。 还公开了用于在动态范围内没有牺牲的情况下改变阵列的灵敏度的手段。

公开(公告)号：US3641405A

公开(公告)日：1972-02-08

申请号：US3641405D

申请日：1969-12-16

Applicant: GEN ELECTRIC

Inventor： BROWN DALE M ,  ENGELER WILLIAM E

IPC: H01L21/225 ,  H01L21/316 ,  H01L27/00 ,  H01L27/092 ,  H01L29/00 ,  H01L11/14

CPC classification number: H01L27/00 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/2255 ,  H01L21/31612 ,  H01L21/31662 ,  H01L27/0927 ,  H01L29/00

Abstract: Improved semiconductor field-effect transistors have selfregistration and electrical insulation. Conductivity-modified, surface adjacent source and drain regions are formed by diffusing dopants through gate-oxide layer. One embodiment features a conducting gate electrode which is formed from a thin deposited film. In this embodiment a large region of opposite-conductivitytype semiconductor is formed by diffusion through both conducting and oxide films. Complementary ''''N-channel'''' and ''''P-channel'''' devices may be formed on the same substrate by combining two separate embodiments. In such devices the original conductivitytype semiconductor is the base for one FET, while the large conductivity-modified-type region is the base for the other FET. Such modules may be interconnected to form integrated circuits capable of performing a variety of logical functions.

Abstract translation: 改进的半导体场效应晶体管具有自动对准和电绝缘。 通过将掺杂剂通过栅氧化层扩散形成电导率改性的表面相邻源极和漏极区。 一个实施例的特征在于由薄的沉积膜形成的导电栅电极。 在本实施例中，通过扩散通过导电和氧化膜形成相反导电型半导体的大区域。 可以通过组合两个单独的实施例在相同的基板上形成互补的“N沟道”和“P沟道”器件。 在这种器件中，原始导电型半导体是一个FET的基极，而大导电率改变型区域是另一个FET的基极。 这样的模块可以互连以形成能够执行各种逻辑功能的集成电路。

公开(公告)号：US3685140A

公开(公告)日：1972-08-22

申请号：US3685140D

申请日：1969-10-03

Applicant: GEN ELECTRIC

Inventor： ENGELER WILLIAM E

IPC: H01L21/00 ,  H01L29/00 ,  H01L29/78 ,  B01J17/00 ,  H01G13/00

CPC classification number: H01L29/7827 ,  H01L21/00 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/66666 ,  H01L2224/48463 ,  Y10S148/053 ,  Y10S148/106 ,  Y10S148/151

Abstract: An improved field-effect transistor having an exceedingly short channel length is described wherein a single edge defines the boundaries of both the source and drain regions. In one embodiment a gate electrode is formed over a thin oxide layer deposited on a semiconductor wafer of a first-conductivity type. An opposite-conductivity type impurity is diffused into the wafer adjacent the gate electrode. A first-conductivity-type impurity is diffused within the opposite-conductivity-type region forming a field-effect transistor having one edge of the gate electrode defining the boundary between the source and channel and the drain and channel regions. In another embodiment an edge of an insulating layer defines the boundaries of the source and drain regions. A method for fabricating isolated resistance elements is also disclosed.

公开(公告)号：US3577045A

公开(公告)日：1971-05-04

申请号：US3577045D

申请日：1968-09-18

Applicant: GEN ELECTRIC

Inventor： ENGELER WILLIAM E ,  GARFINKEL MARVIN

IPC: H01L21/00 ,  H01L21/205 ,  H01L29/00 ,  H01L29/08 ,  H01L3/00

CPC classification number: H01L29/0804 ,  H01L21/00 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L29/00 ,  Y10S148/043 ,  Y10S148/05 ,  Y10S148/151

Abstract: A transistor, such as NPN type, for example, is fabricated by first diffusing a heavily doped P-type base contact region into an N-type semiconductor layer epitaxially grown on a heavily doped N-type semiconductor wafer. Holes are etched through the base contact region into the N-type layer and strongly N-type semiconductor material containing both N-type impurities and faster diffusing P-type impurities is epitaxially grown so as to fill the holes. The wafer is then heated to diffuse the P-type impurities so as to form a base region of controlled thickness, simultaneously forming emitter-base and base-collector junctions. Emitter contact is made by contacting the material epitaxially grown in the holes. Other type semiconductor devices, such as semiconductor controlled rectifiers, may also be fabricated in this manner.

公开(公告)号：US3462223A

公开(公告)日：1969-08-19

申请号：US3462223D

申请日：1965-10-21

Applicant: GEN ELECTRIC

Inventor： TIEMANN JEROME J ,  ENGELER WILLIAM E ,  GARFINKEL MARVIN ,  FRITZSCHE HELLMUT

IPC: G01B11/16 ,  G01L1/24

CPC classification number: G01B11/16 ,  G01L1/24

公开(公告)号：US3921194A

公开(公告)日：1975-11-18

申请号：US37881973

申请日：1973-07-13

Applicant: GEN ELECTRIC

Inventor： ENGELER WILLIAM E ,  TIEMANN JEROME J

IPC: G11C19/18 ,  H01L27/105 ,  H01L29/423 ,  H01L29/768 ,  H01L27/10 ,  H01L29/78

CPC classification number: H01L29/42396 ,  G11C19/186 ,  H01L27/1057 ,  H01L29/76883

Abstract: A method and apparatus for storing and transferring information employing a conductor-insulator-semiconductor (CIS) structure as the storage and transfer apparatus is disclosed herein. The CIS structure is initially charged to a predetermined voltage thereby forming a depletion region within the semiconductor beneath the insulated conductor. Minority carriers controllably generated within the semiconductor are stored at the surface of the semiconductor beneath the insulated conductor by an electric field existing in the depletion region, thus changing the predetermined voltage. Means for transferring the stored charge along the surface of the semiconductor are disclosed.

公开(公告)号：US3890635A

公开(公告)日：1975-06-17

申请号：US42841873

申请日：1973-12-26

Applicant: GEN ELECTRIC

Inventor： ENGELER WILLIAM E

IPC: H01L27/088 ,  H01L29/00 ,  H01L29/94 ,  H01L17/00

CPC classification number: H01L29/94 ,  H01L27/088 ,  H01L29/00

Abstract: A high frequency CIS capacitance device having a substrate of one conductivity type provides a pair of values of capacitance for a high frequency signal applied across a pair of capacitance electrodes thereof. One of the values of capacitance is dependent on applying a control potential on a control electrode to the surface adjacent region underlying one of the capacitance electrodes through a channel region of opposite conductivity and greater in magnitude than the surface potential of the surface adjacent region to drain the surface adjacent region of charge carriers therein. Means are provided for alternatively establishing the channel region to produce one value of capacitance corresponding to depletion of charge carrriers from the surface adjacent region or another value of capacitance corresponding to establishing another value of surface potential in this surface adjacent region by other means. Such other means may be by applying another control potential through another channel region of opposite conductivity or by generation of charge carriers within the substrate. Composite devices are formed of elemental devices such as described in which the capacitance of the composite device is the sum of the capacitance of the elemental devices and is variable in discrete increments to provide a large number of discrete values of capacitance in response to digital signals applied to a minimum number of control electrodes connected thereto.

Abstract translation: 具有一种导电类型的衬底的高频CIS电容器件为跨越其一对电容电极施加的高频信号提供一对电容值。 电容值之一取决于通过相反电导率的沟道区域和控制电极上的相邻区域之间的表面相邻区域施加控制电位，其幅度大于表面相邻区域到漏极的表面电位 其中电荷载体的表面相邻区域。 提供了用于交替地建立通道区域以产生对应于来自表面相邻区域的电荷载流子耗尽的一个电容值或对应于通过其他方式在该表面相邻区域中建立另一表面电位值的另一电容值的装置。 这样的其他手段可以是通过另一个具有相反导电性的沟道区域或通过在衬底内产生电荷载流子施加另一个控制电位。 复合器件​​由诸如所描述的元件器件形成，其中复合器件的电容是元件器件的电容的总和，并且以离散增量可变，以响应于施加的数字信号提供大量的电容离散值 到与其连接的最小数量的控制电极。

公开(公告)号：US3614678A

公开(公告)日：1971-10-19

申请号：US3614678D

申请日：1967-08-11

Applicant: GEN ELECTRIC

Inventor： ENGELER WILLIAM E ,  GARFINKEL MARVIN

IPC: H03H9/54 ,  H03H9/56 ,  H03H9/00

CPC classification number: H03H9/56

Abstract: An electromechanical filter in monolithic silicon integrated circuitry is formed with a resonator member bridging a cavity and having a strain-sensitive piezoresistive pickoff element formed therein. When the resonator member is driven electrostrictively, capacitively, electromagnetically, magnetostrictively or magnetically, an AC output signal is provided by the pickoff element at a frequency dependent upon the mechanical characteristics of the member. The filter is fabricated by burying a silicon nitride slab within an epitaxially formed crystal and thereafter first etching out a pair of regions to define the sides of the resonant member and next etching away the silicon nitride slab to form a cavity beneath the resonator member.

公开(公告)号：US3566518A

公开(公告)日：1971-03-02

申请号：US3566518D

申请日：1967-10-13

Applicant: GEN ELECTRIC

Inventor： BROWN DALE M ,  ENGELER WILLIAM E

IPC: H01L29/78 ,  H01L21/00 ,  H01L21/316 ,  H01L27/00 ,  H01L27/092 ,  H01L29/00 ,  B01J17/00 ,  H01G13/00

CPC classification number: H01L27/00 ,  H01L21/00 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02263 ,  H01L21/31612 ,  H01L21/31662 ,  H01L27/0927 ,  H01L29/00 ,  Y10S148/043 ,  Y10S148/053 ,  Y10S148/103 ,  Y10S148/105 ,  Y10S148/106 ,  Y10S438/923 ,  Y10S438/965

Abstract: IMPROVED SEMICONDUCTOR FIELD-EFFECT TRANSISTORS HAVE SELF-REGISTRATION AND ELECTRICAL INSULATION. CONDUCTIVITYMODIFIED, SURFACE-ADJACENT SOURCE AND DRAIN REGIONS ARE FORMED BY DIFFUSING DOPANTS THROUGH GATE-OXIDE LAYER. ONE EMBODIMENT FEATURES A CONDUCTING GATE ELECTRODE WHICH IS FORMED FROM A THIN DEPOSITED FILM. IN THIS EMBODIMENT A LARGE REGION OF OPPOSITE-CONDUCTIVITY-TYPE SEMICONDUCTOR IS FORMED BY DIFFUSION THROUGH BOTH CONDUCTING AND OXIDE FILMS. COMPLEMENTARY "N-CHANNEL" AND "P-CHANNEL" DEVICES MAY BE FORMED ON THE SAME SUBSTRATE BY COMBINING TWO SEPARATE EMBODIMENTS. IN SUCH DEVICES THE ORIGINAL CONDUCTIVITY-TYPE SEMICONDUCTOR IS THE BASE FOR ONE FET, WHILE THE LARGE CONDUCTIVITY-MODIFIED TYPE REGION IS THE BASE FOR THE OTHER FET. SUCH MODULES MAY BE INTERCONNECTED TO FORM INTEGRATED CIRCUITS CAPABLE OF PERFORMING A VARIETY OF LOGICAL FUNCTIONS.

公开(公告)号：US3566517A

公开(公告)日：1971-03-02

申请号：US3566517D

申请日：1967-10-13

Applicant: GEN ELECTRIC

Inventor： BROWN DALE M ,  ENGELER WILLIAM E ,  GRAY PETER V ,  GARFINKEL MARVIN

IPC: H01L21/00 ,  H01L29/00 ,  H01L29/78 ,  B01J17/00 ,  H01G13/00

CPC classification number: H01L29/00 ,  H01L21/00 ,  H01L29/78 ,  Y10S148/043 ,  Y10S148/053 ,  Y10S148/103 ,  Y10S148/105 ,  Y10S148/106

Abstract: SELF-REGISTERED FIELD-EFFECT TRANSISTORS ARE BUILT BY FORMING THE GATE THEREOF AT THE SAME TIME THE CHANNEL-ADJACENT PORTION OF THE SOURCE AND DRAIN REGIONS ARE DEFINED. IN ONE EMBODIMENT A REFACTORY METALLIC FILM IS DEPOSITED OVER AN INSULATING FILM AND ETCHED TO FORM THE GATE. SUBSEQUENTLY, THE METALLIC FILM MAY SERVE AS A DIFFUSION MASK, ALTHOUGH THIS IS NOT ESSENTIAL. THE METALLIC FILM IS PATTERNED BY PHOTORESIST MASKING AND ETCHING. THE PORTION OF THE METALLIC FILM OVERLYING THE CHANNEL REGION OF THE SEMICONDUCTOR BODY THEREOF IS USED AS A GATE. AS A RESULT OF SIMULTANEOUS DEFINITION OF THE CHANNEL-ADJACENT PLORTIONS OF SOURCE AND DRAIN REGIONS AND PATTERNING OF THE CHANNELALIGNED PORTIONS OF THE GATE, WHEN SOURCE AND DRAIN REGIONS ARE FORMED BY DIFFUSION OF ACTIVATORS INTO THE SILICON WAFER, AUTOMATIC REGISTRATION OF THE GATE-ADJACENT PORTIONS OF THE SOURCE AND DRAIN JUNCTIONS BENEATH THE GATE IS ACHIEVED.