公开(公告)号：US09653571B2

公开(公告)日：2017-05-16

申请号：US14739662

申请日：2015-06-15

Applicant: International Business Machines Corporation ,  Samsung Electronics Co., Ltd. ,  GLOBALFOUNDRIES Inc.

Inventor： Hsueh-Chung Chen ,  Su Chen Fan ,  Dong Kwon Kim ,  Sean Lian ,  Fee Li Lie ,  Linus Jang

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/311 ,  H01L21/02 ,  H01L21/308

CPC classification number: H01L29/6653 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/3086 ,  H01L21/31116

Abstract: An aspect of the invention includes a freestanding spacer having a sub-lithographic dimension for a sidewall image transfer process. The freestanding spacer comprises: a first spacer layer having a first portion disposed on the semiconductor layer; and a second spacer layer having a first surface disposed on the first portion of the first spacer layer, wherein the first spacer layer has a first dielectric constant and the second spacer layer has a second dielectric constant, the first dielectric constant being greater than the second dielectric constant, and wherein a dimension of each of the first and second spacer layers collectively determine the sub-lithographic lateral dimension of the freestanding spacer.

公开(公告)号：US09496257B2

公开(公告)日：2016-11-15

申请号：US14318822

申请日：2014-06-30

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Soon-cheon Seo ,  Linus Jang

IPC: H01L27/088 ,  H01L29/423 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/306 ,  H01L21/027 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/84

CPC classification number: H01L21/30604 ,  H01L21/0274 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/84 ,  H01L27/0886 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/785

Abstract: After semiconductor material portions and gate structures are formed on a substrate, a dielectric material layer is deposited on the semiconductor material portions and the gate structures. An anisotropic etch is performed on the dielectric material layer to form gate spacers, while a mask layer protects peripheral portions of the semiconductor material portions and the gate structures to avoid unwanted physical exposure of semiconductor surfaces. A selective epitaxy can be performed to form raised active regions on the semiconductor material portions. Formation of semiconductor growth defects during the selective epitaxy is prevented by the dielectric material layer. Alternately, a selective semiconductor deposition process can be performed after formation of dielectric gate spacers on gate structures overlying semiconductor material portions. Semiconductor growth defects can be removed by an etch while a mask layer protects raised active regions on the semiconductor material portions.

Abstract translation: 在衬底上形成半导体材料部分和栅极结构之后，在半导体材料部分和栅极结构上沉积介电材料层。 在电介质材料层上进行各向异性蚀刻以形成栅极间隔物，而掩模层保护半导体材料部分和栅极结构的外围部分以避免半导体表面的不期望的物理暴露。 可以进行选择性外延以在半导体材料部分上形成凸起的有源区。 通过介电材料层可以防止选择性外延期间的半导体生长缺陷的形成。 或者，可以在覆盖半导体材料部分的栅极结构上形成介电栅极间隔物之后执行选择性半导体沉积工艺。 半导体生长缺陷可以通过蚀刻去除，而掩模层保护半导体材料部分上的凸起的有源区。

公开(公告)号：US20160064236A1

公开(公告)日：2016-03-03

申请号：US14935767

申请日：2015-11-09

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Linus Jang ,  Soon-Cheon Seo ,  Ryan O. Jung

IPC: H01L21/308 ,  H01L29/66 ,  H01L21/283

CPC classification number: H01L21/3085 ,  H01L21/0337 ,  H01L21/28141 ,  H01L21/283 ,  H01L21/3081 ,  H01L21/32139 ,  H01L21/82385 ,  H01L29/6656

Abstract: A method includes forming a layer of material above a semiconductor substrate and performing a first sidewall image transfer process to form a first plurality of spacers and a second plurality of spacers above the layer of material, wherein the first and second pluralities of spacers are positioned above respective first and second regions of the semiconductor substrate and have a same initial width and a same pitch spacing. A masking layer is formed above the layer of material so as to cover the first plurality of spacers and expose the second plurality of spacers, and a first etching process is performed through the masking layer on the exposed second plurality of spacers so as to form a plurality of reduced-width spacers having a width that is less than the initial width, wherein the first plurality of spacers and the plurality of reduced-width spacers define an etch mask.

Abstract translation: 一种方法包括在半导体衬底上形成材料层并执行第一侧壁图像转移工艺以在材料层之上形成第一多个间隔物和第二多个间隔物，其中第一和第二多个间隔物位于 相应的半导体衬底的第一和第二区域，并且具有相同的初始宽度和相同的间距间距。 在材料层的上方形成掩模层，以便覆盖第一多个间隔物并露出第二多个间隔物，并且通过暴露的第二多个间隔物上的掩模层进行第一蚀刻工艺，从而形成 多个宽度窄于所述初始宽度的宽度窄的间隔物，其中所述第一多个间隔物和所述多个减小宽度的间隔物限定蚀刻掩模。

公开(公告)号：US09214360B2

公开(公告)日：2015-12-15

申请号：US13874577

申请日：2013-05-01

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Linus Jang ,  Soon-Cheon Seo ,  Ryan O. Jung

IPC: H01L21/311 ,  H01L21/3213 ,  H01L21/033 ,  H01L21/28 ,  H01L21/8238

CPC classification number: H01L21/3085 ,  H01L21/0337 ,  H01L21/28141 ,  H01L21/283 ,  H01L21/3081 ,  H01L21/32139 ,  H01L21/82385 ,  H01L29/6656

Abstract: Disclosed herein are methods of patterning features that have differing widths. In one example, the method includes forming a layer of material above a semiconductor substrate, forming a masking layer above the layer of material, wherein the masking layer is comprised of a first plurality features positioned above a first region of the semiconductor substrate and a second plurality of features positioned above a second region of the semiconductor substrate, wherein the first and second plurality of features have the same pitch spacing and wherein the first and second plurality of features have different widths, and performing at least one etching process on the layer of material through the masking layer.

Abstract translation: 本文公开了具有不同宽度的图案特征的方法。 在一个示例中，该方法包括在半导体衬底之上形成材料层，在材料层之上形成掩模层，其中掩模层由位于半导体衬底的第一区域上方的第一多个特征构成，第二 多个特征位于所述半导体衬底的第二区域之上，其中所述第一和第二多个特征具有相同的间距间距，并且其中所述第一和第二多个特征具有不同的宽度，并且对所述第一和第二多个特征层进行至少一个蚀刻处理 材料通过掩模层。

公开(公告)号：US09653573B2

公开(公告)日：2017-05-16

申请号：US14827510

申请日：2015-08-17

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Linus Jang ,  Sivananda K. Kanakasabapathy ,  Sanjay C. Mehta ,  Soon-Cheon Seo ,  Raghavasimhan Sreenivasan

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/311

CPC classification number: H01L29/66545 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/6656 ,  H01L29/66795

Abstract: A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer disposed on the fin. The plurality of gate formation layers include a dummy gate layer formed from a dielectric material. The plurality of gate formation layers is patterned to form a plurality of dummy gate elements on the etch stop layer. Each dummy gate element is formed from the dielectric material. A spacer layer formed on the dummy gate elements is etched to form a spacer on each sidewall of dummy gate elements. A portion of the etch stop layer located between each dummy gate element is etched to expose a portion the semiconductor fin. A semiconductor material is epitaxially grown from the exposed portion of the semiconductor fin to form source/drain regions.

公开(公告)号：US20150380405A1

公开(公告)日：2015-12-31

申请号：US14318822

申请日：2014-06-30

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Soon-cheon Seo ,  Linus Jang

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/306 ,  H01L29/423 ,  H01L21/311

CPC classification number: H01L21/30604 ,  H01L21/0274 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/84 ,  H01L27/0886 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/785

Abstract: After semiconductor material portions and gate structures are formed on a substrate, a dielectric material layer is deposited on the semiconductor material portions and the gate structures. An anisotropic etch is performed on the dielectric material layer to form gate spacers, while a mask layer protects peripheral portions of the semiconductor material portions and the gate structures to avoid unwanted physical exposure of semiconductor surfaces. A selective epitaxy can be performed to form raised active regions on the semiconductor material portions. Formation of semiconductor growth defects during the selective epitaxy is prevented by the dielectric material layer. Alternately, a selective semiconductor deposition process can be performed after formation of dielectric gate spacers on gate structures overlying semiconductor material portions. Semiconductor growth defects can be removed by an etch while a mask layer protects raised active regions on the semiconductor material portions.

Abstract translation: 在衬底上形成半导体材料部分和栅极结构之后，在半导体材料部分和栅极结构上沉积介电材料层。 在电介质材料层上进行各向异性蚀刻以形成栅极间隔物，而掩模层保护半导体材料部分和栅极结构的外围部分以避免半导体表面的不期望的物理暴露。 可以进行选择性外延以在半导体材料部分上形成凸起的有源区。 通过介电材料层可以防止选择性外延期间的半导体生长缺陷的形成。 或者，可以在覆盖半导体材料部分的栅极结构上形成介电栅极间隔物之后执行选择性半导体沉积工艺。 半导体生长缺陷可以通过蚀刻去除，而掩模层保护半导体材料部分上的凸起的有源区。

公开(公告)号：US20140329388A1

公开(公告)日：2014-11-06

申请号：US13874577

申请日：2013-05-01

Applicant: GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Linus Jang ,  Soon-Cheon Seo ,  Ryan O. Jung

IPC: H01L21/311

CPC classification number: H01L21/3085 ,  H01L21/0337 ,  H01L21/28141 ,  H01L21/283 ,  H01L21/3081 ,  H01L21/32139 ,  H01L21/82385 ,  H01L29/6656

Abstract: Disclosed herein are methods of patterning features that have differing widths. In one example, the method includes forming a layer of material above a semiconductor substrate, forming a masking layer above the layer of material, wherein the masking layer is comprised of a first plurality features positioned above a first region of the semiconductor substrate and a second plurality of features positioned above a second region of the semiconductor substrate, wherein the first and second plurality of features have the same pitch spacing and wherein the first and second plurality of features have different widths, and performing at least one etching process on the layer of material through the masking layer.

Abstract translation: 本文公开了具有不同宽度的图案特征的方法。 在一个示例中，该方法包括在半导体衬底之上形成材料层，在材料层之上形成掩模层，其中掩模层由位于半导体衬底的第一区域上方的第一多个特征构成，第二 多个特征位于所述半导体衬底的第二区域之上，其中所述第一和第二多个特征具有相同的间距间距，并且其中所述第一和第二多个特征具有不同的宽度，并且对所述第一和第二多个特征层进行至少一个蚀刻处理 材料通过掩模层。

公开(公告)号：US09466505B2

公开(公告)日：2016-10-11

申请号：US14935767

申请日：2015-11-09

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Linus Jang ,  Soon-Cheon Seo ,  Ryan O. Jung

IPC: H01L21/311 ,  H01L21/308 ,  H01L21/033 ,  H01L21/3213 ,  H01L21/28 ,  H01L21/8238 ,  H01L21/283 ,  H01L29/66

CPC classification number: H01L21/3085 ,  H01L21/0337 ,  H01L21/28141 ,  H01L21/283 ,  H01L21/3081 ,  H01L21/32139 ,  H01L21/82385 ,  H01L29/6656

Abstract: A method includes forming a layer of material above a semiconductor substrate and performing a first sidewall image transfer process to form a first plurality of spacers and a second plurality of spacers above the layer of material, wherein the first and second pluralities of spacers are positioned above respective first and second regions of the semiconductor substrate and have a same initial width and a same pitch spacing. A masking layer is formed above the layer of material so as to cover the first plurality of spacers and expose the second plurality of spacers, and a first etching process is performed through the masking layer on the exposed second plurality of spacers so as to form a plurality of reduced-width spacers having a width that is less than the initial width, wherein the first plurality of spacers and the plurality of reduced-width spacers define an etch mask.

Abstract translation: 一种方法包括在半导体衬底上形成材料层并执行第一侧壁图像转移工艺以在材料层之上形成第一多个间隔物和第二多个间隔物，其中第一和第二多个间隔物位于 相应的半导体衬底的第一和第二区域，并且具有相同的初始宽度和相同的间距间距。 在材料层的上方形成掩模层，以便覆盖第一多个间隔物并露出第二多个间隔物，并且通过暴露的第二多个间隔物上的掩模层进行第一蚀刻工艺，从而形成 多个宽度窄于所述初始宽度的宽度窄的间隔物，其中所述第一多个间隔物和所述多个减小宽度的间隔物限定蚀刻掩模。

公开(公告)号：US20160172467A1

公开(公告)日：2016-06-16

申请号：US15062465

申请日：2016-03-07

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Linus Jang ,  Sivananda K. Kanakasabapathy ,  Sanjay C. Mehta ,  Soon-Cheon Seo ,  Raghavasimhan Sreenivasan

IPC: H01L29/66 ,  H01L21/3065 ,  H01L21/8234 ,  H01L21/283

CPC classification number: H01L29/66545 ,  H01L21/02164 ,  H01L21/2018 ,  H01L21/28238 ,  H01L21/3065 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7855 ,  H01L2029/7858

Abstract: A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer disposed on the fin. The plurality of gate formation layers include a dummy gate layer formed from a dielectric material. The plurality of gate formation layers is patterned to form a plurality of dummy gate elements on the etch stop layer. Each dummy gate element is formed from the dielectric material. A spacer layer formed on the dummy gate elements is etched to form a spacer on each sidewall of dummy gate elements. A portion of the etch stop layer located between each dummy gate element is etched to expose a portion the semiconductor fin. A semiconductor material is epitaxially grown from the exposed portion of the semiconductor fin to form source/drain regions.

公开(公告)号：US20150357434A1

公开(公告)日：2015-12-10

申请号：US14827510

申请日：2015-08-17

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Linus Jang ,  Sivananda K. Kanakasabapathy ,  Sanjay C. Mehta ,  Soon-Cheon Seo ,  Raghavasimhan Sreenivasan

IPC: H01L29/66 ,  H01L21/3065 ,  H01L21/283

CPC classification number: H01L29/66545 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/6656 ,  H01L29/66795

Abstract: A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer disposed on the fin. The plurality of gate formation layers include a dummy gate layer formed from a dielectric material. The plurality of gate formation layers is patterned to form a plurality of dummy gate elements on the etch stop layer. Each dummy gate element is formed from the dielectric material. A spacer layer formed on the dummy gate elements is etched to form a spacer on each sidewall of dummy gate elements. A portion of the etch stop layer located between each dummy gate element is etched to expose a portion the semiconductor fin. A semiconductor material is epitaxially grown from the exposed portion of the semiconductor fin to form source/drain regions.