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公开(公告)号:US08217513B2
公开(公告)日:2012-07-10
申请号:US13019854
申请日:2011-02-02
申请人: George Andrew Antonelli , Jennifer O'Loughlin , Tony Xavier , Mandyam Sriram , Bart van Schravendijk , Vishwanathan Rangarajan , Seshasayee Varadarajan , Bryan L. Buckalew
发明人: George Andrew Antonelli , Jennifer O'Loughlin , Tony Xavier , Mandyam Sriram , Bart van Schravendijk , Vishwanathan Rangarajan , Seshasayee Varadarajan , Bryan L. Buckalew
IPC分类号: H01L23/34
CPC分类号: H01L21/02068 , C23C16/0245 , C23C16/54 , C23C16/56 , H01L21/0206 , H01L21/02074 , H01L21/02315 , H01L21/3105 , H01L21/67201 , H01L21/76826 , H01L21/76862 , H01L21/76883 , H01L2924/0002 , H01L2924/00
摘要: Embodiments related to the cleaning of interface surfaces in a semiconductor wafer fabrication process via remote plasma processing are disclosed herein. For example, in one disclosed embodiment, a semiconductor processing apparatus includes a processing chamber, a load lock coupled to the processing chamber via a transfer port, a wafer pedestal disposed in the load lock and configured to support a wafer in the load lock, a remote plasma source configured to provide a remote plasma to the load lock, and an ion filter disposed between the remote plasma source and the wafer pedestal.
摘要翻译: 本文公开了通过远程等离子体处理在半导体晶片制造工艺中清洁界面的实施例。 例如,在一个所公开的实施例中,半导体处理装置包括处理室,经由传送端口与处理室耦合的负载锁定,设置在负载锁中并被配置为支撑加载锁中的晶片的晶片基座, 远程等离子体源,被配置为将远程等离子体提供给负载锁定;以及离子过滤器,其布置在远程等离子体源和晶片基座之间。
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公开(公告)号:US08084339B2
公开(公告)日:2011-12-27
申请号:US12484047
申请日:2009-06-12
申请人: George Andrew Antonelli , Jennifer O'Loughlin , Tony Xavier , Mandyam Sriram , Bart Van Schravendijk , Vishwanathan Rangarajan , Seshasayee Varadarajan , Bryan L. Buckalew
发明人: George Andrew Antonelli , Jennifer O'Loughlin , Tony Xavier , Mandyam Sriram , Bart Van Schravendijk , Vishwanathan Rangarajan , Seshasayee Varadarajan , Bryan L. Buckalew
IPC分类号: H01L21/261
CPC分类号: H01L21/02068 , C23C16/0245 , C23C16/54 , C23C16/56 , H01L21/0206 , H01L21/02074 , H01L21/02315 , H01L21/3105 , H01L21/67201 , H01L21/76826 , H01L21/76862 , H01L21/76883 , H01L2924/0002 , H01L2924/00
摘要: Embodiments related to the cleaning of interface surfaces in a semiconductor wafer fabrication process via remote plasma processing are disclosed herein. For example, in one disclosed embodiment, a semiconductor processing apparatus includes a processing chamber, a load lock coupled to the processing chamber via a transfer port, a wafer pedestal disposed in the load lock and configured to support a wafer in the load lock, a remote plasma source configured to provide a remote plasma to the load lock, and an ion filter disposed between the remote plasma source and the wafer pedestal.
摘要翻译: 本文公开了通过远程等离子体处理在半导体晶片制造工艺中清洁界面的实施例。 例如,在一个所公开的实施例中,半导体处理装置包括处理室,经由传送端口与处理室耦合的负载锁定,设置在负载锁中并被配置为支撑加载锁中的晶片的晶片基座, 远程等离子体源,被配置为将远程等离子体提供给负载锁定;以及离子过滤器,其布置在远程等离子体源和晶片基座之间。
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公开(公告)号:US20110120377A1
公开(公告)日:2011-05-26
申请号:US13019854
申请日:2011-02-02
申请人: George Andrew Antonelli , Jennifer O'Loughlin , Tony Xavier , Mandyam Sriram , Bart Van Schravendijk , Vishwanathan Rangarajan , Seshasayee Varadarajan , Bryan L. Buckalew
发明人: George Andrew Antonelli , Jennifer O'Loughlin , Tony Xavier , Mandyam Sriram , Bart Van Schravendijk , Vishwanathan Rangarajan , Seshasayee Varadarajan , Bryan L. Buckalew
IPC分类号: H01L21/4763
CPC分类号: H01L21/02068 , C23C16/0245 , C23C16/54 , C23C16/56 , H01L21/0206 , H01L21/02074 , H01L21/02315 , H01L21/3105 , H01L21/67201 , H01L21/76826 , H01L21/76862 , H01L21/76883 , H01L2924/0002 , H01L2924/00
摘要: Embodiments related to the cleaning of interface surfaces in a semiconductor wafer fabrication process via remote plasma processing are disclosed herein. For example, in one disclosed embodiment, a semiconductor processing apparatus comprises a processing chamber, a load lock coupled to the processing chamber via a transfer port, a wafer pedestal disposed in the load lock and configured to support a wafer in the load lock, a remote plasma source configured to provide a remote plasma to the load lock, and an ion filter disposed between the remote plasma source and the wafer pedestal.
摘要翻译: 本文公开了通过远程等离子体处理在半导体晶片制造工艺中清洁界面的实施例。 例如,在一个所公开的实施例中,半导体处理装置包括处理室,经由传送端口耦合到处理室的负载锁,设置在负载锁中并被配置为支撑加载锁中的晶片的晶片基座, 远程等离子体源,被配置为将远程等离子体提供给负载锁定;以及离子过滤器,其布置在远程等离子体源和晶片基座之间。
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公开(公告)号:US20100317198A1
公开(公告)日:2010-12-16
申请号:US12533960
申请日:2009-07-31
申请人: George Andrew Antonelli , Jennifer O' Loughlin , Tony Xavier , Mandyam Sriram , Bart van Schravendijk , Vishwanathan Rangarajan , Seshasayee Varadarajan , Bryan L. Buckalew
发明人: George Andrew Antonelli , Jennifer O' Loughlin , Tony Xavier , Mandyam Sriram , Bart van Schravendijk , Vishwanathan Rangarajan , Seshasayee Varadarajan , Bryan L. Buckalew
IPC分类号: H01L21/465 , C23C16/50
CPC分类号: H01L21/02074 , C23C16/0245 , C23C16/54 , H01L21/0206 , H01L21/28185 , H01L21/3105 , H01L21/67201 , H01L21/76814 , H01L21/76825 , H01L21/76826 , H01L21/76829 , H01L21/76834 , H01L21/76886 , H01L28/60
摘要: Embodiments related to the cleaning of interface surfaces in a semiconductor wafer fabrication process via remote plasma processing are disclosed herein. For example, in one disclosed embodiment, a semiconductor processing apparatus comprises a processing chamber, a load lock coupled to the processing chamber via a transfer port, a wafer pedestal disposed in the load lock and configured to support a wafer in the load lock, and a remote plasma source configured to provide a remote plasma to the load lock.
摘要翻译: 本文公开了通过远程等离子体处理在半导体晶片制造工艺中清洁界面的实施例。 例如,在一个所公开的实施例中,半导体处理装置包括处理室,经由传送端口耦合到处理室的负载锁定,设置在负载锁中并被配置为支撑加载锁中的晶片的晶片基座,以及 远程等离子体源,被配置为向负载锁提供远程等离子体。
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公开(公告)号:US20100317178A1
公开(公告)日:2010-12-16
申请号:US12484047
申请日:2009-06-12
申请人: George Andrew Antonelli , Jennifer O' Loughlin , Tony Xavier , Mandyam Sriram , Bart Van Schravendijk , Vishwanathan Rangarajan , Seshasayee Varadarajan , Bryan L. Buckalew
发明人: George Andrew Antonelli , Jennifer O' Loughlin , Tony Xavier , Mandyam Sriram , Bart Van Schravendijk , Vishwanathan Rangarajan , Seshasayee Varadarajan , Bryan L. Buckalew
IPC分类号: H01L21/3205 , C23C16/513 , C23C16/02 , H01L21/31
CPC分类号: H01L21/02068 , C23C16/0245 , C23C16/54 , C23C16/56 , H01L21/0206 , H01L21/02074 , H01L21/02315 , H01L21/3105 , H01L21/67201 , H01L21/76826 , H01L21/76862 , H01L21/76883 , H01L2924/0002 , H01L2924/00
摘要: Embodiments related to the cleaning of interface surfaces in a semiconductor wafer fabrication process via remote plasma processing are disclosed herein. For example, in one disclosed embodiment, a semiconductor processing apparatus comprises a processing chamber, a load lock coupled to the processing chamber via a transfer port, a wafer pedestal disposed in the load lock and configured to support a wafer in the load lock, a remote plasma source configured to provide a remote plasma to the load lock, and an ion filter disposed between the remote plasma source and the wafer pedestal.
摘要翻译: 本文公开了通过远程等离子体处理在半导体晶片制造工艺中清洁界面的实施例。 例如,在一个所公开的实施例中,半导体处理装置包括处理室,经由传送端口耦合到处理室的负载锁,设置在负载锁中并被配置为支撑加载锁中的晶片的晶片基座, 远程等离子体源,被配置为将远程等离子体提供给负载锁定;以及离子过滤器,其布置在远程等离子体源和晶片基座之间。
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公开(公告)号:US08536073B2
公开(公告)日:2013-09-17
申请号:US13546937
申请日:2012-07-11
IPC分类号: H01L21/311 , H01L21/461 , H01L21/469
CPC分类号: H01L21/02274 , C23C16/30 , C23C16/325 , C23C16/34 , C23C16/505 , C23C16/56 , H01J37/32091 , H01J37/32165 , H01L21/02112 , H01L21/02167 , H01L21/022 , H01L21/0332 , H01L21/31144 , H01L21/3148 , H01L21/318 , H01L21/32139 , H01L21/67017 , H01L21/76813 , Y10S438/932 , Y10S438/942
摘要: Hardmask films having high hardness and low stress are provided. In some embodiments a film has a stress of between about −600 MPa and 600 MPa and hardness of at least about 12 GPa. In some embodiments, a hardmask film is prepared by depositing multiple sub-layers of doped or undoped silicon carbide using multiple densifying plasma post-treatments in a PECVD process chamber. In some embodiments, a hardmask film includes a high-hardness boron-containing film selected from the group consisting of SixByCz, SixByNz, SixByCzNw, BxCy, and BxNy. In some embodiments, a hardmask film includes a germanium-rich GeNx material comprising at least about 60 atomic % of germanium. These hardmasks can be used in a number of back-end and front-end processing schemes in integrated circuit fabrication.
摘要翻译: 提供具有高硬度和低应力的硬掩模薄膜。 在一些实施方案中,膜具有在约-600MPa和600MPa之间的应力以及至少约12GPa的硬度。 在一些实施例中,通过在PECVD处理室中使用多个致密等离子体后处理沉积多个掺杂或未掺杂碳化硅的子层来制备硬掩模膜。 在一些实施例中,硬掩模膜包括选自SixByCz,SixByNz,SixByCzNw,BxCy和BxNy的高硬度含硼膜。 在一些实施例中,硬掩模膜包括富含锗的GeN x材料,其包含至少约60原子%的锗。 这些硬掩模可用于集成电路制造中的许多后端和前端处理方案。
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公开(公告)号:US20110135557A1
公开(公告)日:2011-06-09
申请号:US12631691
申请日:2009-12-04
CPC分类号: H01L21/02274 , C23C16/30 , C23C16/325 , C23C16/34 , C23C16/505 , C23C16/56 , H01J37/32091 , H01J37/32165 , H01L21/02112 , H01L21/02167 , H01L21/022 , H01L21/0332 , H01L21/31144 , H01L21/3148 , H01L21/318 , H01L21/32139 , H01L21/67017 , H01L21/76813 , Y10S438/932 , Y10S438/942
摘要: Hardmask films having high hardness and low stress are provided. In some embodiments a film has a stress of between about −600 MPa and 600 MPa and hardness of at least about 12 GPa. In some embodiments, a hardmask film is prepared by depositing multiple sub-layers of doped or undoped silicon carbide using multiple densifying plasma post-treatments in a PECVD process chamber. In some embodiments, a hardmask film includes a high-hardness boron-containing film selected from the group consisting of SixByCz, SixByNz, SixByCzNw, BxCy, and BxNy. In some embodiments, a hardmask film includes a germanium-rich GeNx material comprising at least about 60 atomic % of germanium. These hardmasks can be used in a number of back-end and front-end processing schemes in integrated circuit fabrication.
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公开(公告)号:US08247332B2
公开(公告)日:2012-08-21
申请号:US12631691
申请日:2009-12-04
IPC分类号: H01L21/311 , H01L21/461 , H01L21/469
CPC分类号: H01L21/02274 , C23C16/30 , C23C16/325 , C23C16/34 , C23C16/505 , C23C16/56 , H01J37/32091 , H01J37/32165 , H01L21/02112 , H01L21/02167 , H01L21/022 , H01L21/0332 , H01L21/31144 , H01L21/3148 , H01L21/318 , H01L21/32139 , H01L21/67017 , H01L21/76813 , Y10S438/932 , Y10S438/942
摘要: Hardmask films having high hardness and low stress are provided. In some embodiments a film has a stress of between about −600 MPa and 600 MPa and hardness of at least about 12 GPa. In some embodiments, a hardmask film is prepared by depositing multiple sub-layers of doped or undoped silicon carbide using multiple densifying plasma post-treatments in a PECVD process chamber. In some embodiments, a hardmask film includes a high-hardness boron-containing film selected from the group consisting of SixByCz, SixByNz, SixByCzNw, BxCy, and BxNy. In some embodiments, a hardmask film includes a germanium-rich GeNx material comprising at least about 60 atomic % of germanium. These hardmasks can be used in a number of back-end and front-end processing schemes in integrated circuit fabrication.
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公开(公告)号:US08178443B2
公开(公告)日:2012-05-15
申请号:US12631709
申请日:2009-12-04
IPC分类号: H01L21/302 , H01L21/00
CPC分类号: H01L21/31144 , C23C16/30 , C23C16/325 , C23C16/34 , C23C16/505 , C23C16/56 , H01J37/32091 , H01J37/32165 , H01L21/02112 , H01L21/02167 , H01L21/022 , H01L21/02274 , H01L21/0332 , H01L21/3148 , H01L21/318 , H01L21/32139 , H01L21/76813
摘要: Hardmask films having high hardness and low stress are provided. In some embodiments a film has a stress of between about −600 MPa and 600 MPa and hardness of at least about 12 GPa. In some embodiments, a hardmask film is prepared by depositing multiple sub-layers of doped or undoped silicon carbide using multiple densifying plasma post-treatments in a PECVD process chamber. In some embodiments, a hardmask film includes a high-hardness boron-containing film selected from the group consisting of SixByCz, SixByNz, SixByCzNw, BxCy, and BxNy. In some embodiments, a hardmask film includes a germanium-rich GeNx material comprising at least about 60 atomic % of germanium. These hardmasks can be used in a number of back-end and front-end processing schemes in integrated circuit fabrication.
摘要翻译: 提供具有高硬度和低应力的硬掩模薄膜。 在一些实施方案中,膜具有在约-600MPa和600MPa之间的应力以及至少约12GPa的硬度。 在一些实施例中,通过在PECVD处理室中使用多个致密等离子体后处理沉积多个掺杂或未掺杂碳化硅的子层来制备硬掩模膜。 在一些实施例中,硬掩模膜包括选自SixByCz,SixByNz,SixByCzNw,BxCy和BxNy的高硬度含硼膜。 在一些实施例中,硬掩模膜包括富含锗的GeN x材料,其包含至少约60原子%的锗。 这些硬掩模可用于集成电路制造中的许多后端和前端处理方案。
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公开(公告)号:US20130008378A1
公开(公告)日:2013-01-10
申请号:US13615318
申请日:2012-09-13
IPC分类号: C23C16/52
CPC分类号: H01L21/02112 , C23C16/342 , C23C16/56 , H01L21/02271 , H01L21/02304 , H01L21/02315 , H01L21/0234 , H01L29/4983 , H01L29/517 , H01L29/665 , H01L29/7843
摘要: A method of forming a boron nitride or boron carbon nitride dielectric produces a conformal layer without loading effect. The dielectric layer is formed by chemical vapor deposition (CVD) of a boron-containing film on a substrate, at least a portion of the deposition being conducted without plasma, and then exposing the deposited boron-containing film to a plasma. The CVD component dominates the deposition process, producing a conformal film without loading effect. The dielectric is ashable, and can be removed with a hydrogen plasma without impacting surrounding materials. The dielectric has a much lower wet etch rate compared to other front end spacer or hard mask materials such as silicon oxide or silicon nitride, and has a relatively low dielectric constant, much lower then silicon nitride.
摘要翻译: 形成氮化硼或氮化硼介质的方法产生没有负载效应的共形层。 介电层通过基板上的含硼膜的化学气相沉积(CVD)形成,至少部分沉积不经等离子体进行,然后将沉积的含硼膜暴露于等离子体。 CVD组件主导沉积过程,产生不带负载效应的保形膜。 电介质是可灰化的,并且可以用氢等离子体除去而不会影响周围的材料。 与其它前端隔离物或诸如氧化硅或氮化硅的硬掩模材料相比,电介质具有低得多的湿蚀刻速率,并且具有比氮化硅低得多的介电常数。
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