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公开(公告)号：US06737365B1
公开(公告)日：2004-05-18
申请号：US10395447
申请日：2003-03-24
IPC分类号： H01L2131
CPC分类号： H01L21/02126 , H01L21/02203 , H01L21/02304 , H01L21/02351 , H01L21/31695 , H01L21/7682
摘要： A dielectric layer is made porous by treating the dielectric material after metal interconnects are formed in or through that layer. The porosity lowers the dielectric constant of the dielectric material. The dielectric material may be subjected to an electron beam or a sonication bath to create the pores. The structure has smooth sidewalls for metal interconnects extending through the dielectric layer.
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公开(公告)号：US07034399B2
公开(公告)日：2006-04-25
申请号：US10782329
申请日：2004-02-19
CPC分类号： H01L21/02126 , H01L21/02203 , H01L21/02304 , H01L21/02351 , H01L21/31695 , H01L21/7682
摘要： A dielectric layer is made porous by treating the dielectric material after metal interconnects are formed in or through that layer. The porosity lowers the dielectric constant of the dielectric material. The dielectric material may be subjected to an electron beam or a sonication bath to create the pores. The structure has smooth sidewalls for metal interconnects extending through the dielectric layer.
摘要翻译： 通过在金属互连形成在该层中或通过该层之后处理介电材料，使介质层多孔化。 孔隙率降低介电材料的介电常数。 介电材料可以经受电子束或超声处理浴以产生孔。 该结构具有延伸穿过介电层的金属互连的平滑侧壁。
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3.发明授权Capping of copper structures in hydrophobic ILD using aqueous electro-less bath 失效在疏水性ILD中使用无水电镀浴封闭铜结构公开(公告)号：US07119019B2
公开(公告)日：2006-10-10
申请号：US10814592
申请日：2004-03-31
申请人： Kevin P. O'Brien , Justin K. Brask
发明人： Kevin P. O'Brien , Justin K. Brask
IPC分类号： H01L21/44 , H01L21/31 , H01L21/469
CPC分类号： H01L21/76849 , C23C18/161 , C23C18/1619 , C23C18/1632 , C23C18/1666 , C23C18/31 , H01L21/288
摘要： Capping of copper structures in hydrophobic interlayer dielectric layer, using aqueous electro-less bath is described herein.
摘要翻译： 本文描述了使用水性无电极浴来疏水层间介电层中铜结构的封盖。
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4.发明授权公开(公告)号：US09048314B2
公开(公告)日：2015-06-02
申请号：US14465636
申请日：2014-08-21
申请人： Robert S. Chau , Suman Datta , Jack Kavalieros , Justin K. Brask , Mark L. Doczy , Matthew Metz
发明人： Robert S. Chau , Suman Datta , Jack Kavalieros , Justin K. Brask , Mark L. Doczy , Matthew Metz
IPC分类号： H01L29/66 , H01L29/78 , H01L29/786 , H01L29/267 , H01L29/10 , H01L29/20 , H01L29/423 , H01L29/51
CPC分类号： H01L29/7848 , H01L29/0649 , H01L29/0847 , H01L29/1033 , H01L29/16 , H01L29/20 , H01L29/201 , H01L29/207 , H01L29/267 , H01L29/41783 , H01L29/4236 , H01L29/452 , H01L29/517 , H01L29/66522 , H01L29/66628 , H01L29/66636 , H01L29/66795 , H01L29/78 , H01L29/7827 , H01L29/7836 , H01L29/785 , H01L29/78603 , H01L29/78618 , H01L29/78681
摘要： A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.
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5.发明申请公开(公告)号：US20130264642A1
公开(公告)日：2013-10-10
申请号：US13908858
申请日：2013-06-03
申请人： Uday Shah , Brian S. Doyle , Justin K. Brask , Robert S. Chau , Thomas A. Letson
发明人： Uday Shah , Brian S. Doyle , Justin K. Brask , Robert S. Chau , Thomas A. Letson
IPC分类号： H01L29/78
CPC分类号： H01L29/42384 , H01L21/823431 , H01L21/845 , H01L27/0886 , H01L27/1211 , H01L29/66795 , H01L29/66818 , H01L29/785 , H01L29/7853 , H01L29/7854 , H01L29/7856 , H01L2924/13067 , Y10S438/978
摘要： A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.
摘要翻译： 具有形成在基板的绝缘层上的半导体本体的非平面半导体器件。 半导体本体具有与形成在绝缘层上的底表面相对的顶表面和一对横向相对的侧壁，其中在顶表面处的横向相对侧壁之间的距离大于底表面处的距离。 栅电介质层形成在半导体本体的顶表面和半导体本体的侧壁上。 栅极电极形成在半导体本体的顶表面和侧壁上的栅介质层上。 在栅电极的相对侧的半导体本体中形成一对源极/漏极区域。
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6.发明申请公开(公告)号：US20130146945A1
公开(公告)日：2013-06-13
申请号：US13752272
申请日：2013-01-28
申请人： Robert S. Chau , Suman Datta , Jack Kavalieros , Justin K. Brask , Mark L. Doczy , Matthew Metz
发明人： Robert S. Chau , Suman Datta , Jack Kavalieros , Justin K. Brask , Mark L. Doczy , Matthew Metz
IPC分类号： H01L29/267
CPC分类号： H01L29/7848 , H01L29/0649 , H01L29/0847 , H01L29/1033 , H01L29/16 , H01L29/20 , H01L29/201 , H01L29/207 , H01L29/267 , H01L29/41783 , H01L29/4236 , H01L29/452 , H01L29/517 , H01L29/66522 , H01L29/66628 , H01L29/66636 , H01L29/66795 , H01L29/78 , H01L29/7827 , H01L29/7836 , H01L29/785 , H01L29/78603 , H01L29/78618 , H01L29/78681
摘要： A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.
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7.发明授权CMOS devices with a single work function gate electrode and method of fabrication 有权CMOS器件具有单功能功能的栅电极和制造方法公开(公告)号：US08294180B2
公开(公告)日：2012-10-23
申请号：US13038190
申请日：2011-03-01
申请人： Brian S. Doyle , Been-Yih Jin , Jack T. Kavalieros , Suman Datta , Justin K. Brask , Robert S. Chau
发明人： Brian S. Doyle , Been-Yih Jin , Jack T. Kavalieros , Suman Datta , Justin K. Brask , Robert S. Chau
IPC分类号： H01L29/66
CPC分类号： H01L21/845 , H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L27/1211 , H01L29/0673 , H01L29/068 , H01L29/1054 , H01L29/66439 , H01L29/66795 , H01L29/775 , H01L29/785
摘要： Described herein are a device utilizing a gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby. Further described herein are methods of fabricating a device formed of complementary (pMOS and nMOS) transistors having semiconductor channel regions which have been band gap engineered to achieve a low threshold voltage.
摘要翻译： 这里描述了利用具有单功函数的栅电极材料的器件，用于pMOS和nMOS晶体管，其中晶体管阈值电压的幅度由半导体带工程和由此制成的制品修改。 本文进一步描述的是制造由互补（pMOS和nMOS）晶体管形成的器件的方法，该晶体管具有被设计成能够实现低阈值电压的带隙的半导体沟道区。
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8.发明申请FIELD EFFECT TRANSISTOR WITH NARROW BANDGAP SOURCE AND DRAIN REGIONS AND METHOD OF FABRICATION 有权具有窄带源和漏区的场效应晶体管和制造方法公开(公告)号：US20120205729A1
公开(公告)日：2012-08-16
申请号：US13453403
申请日：2012-04-23
申请人： Robert S. Chau , Suman Datta , Jack Kavalieros , Justin K. Brask , Mark L. Doczy , Matthew Metz
发明人： Robert S. Chau , Suman Datta , Jack Kavalieros , Justin K. Brask , Mark L. Doczy , Matthew Metz
IPC分类号： H01L29/772
CPC分类号： H01L29/7848 , H01L29/0649 , H01L29/0847 , H01L29/1033 , H01L29/16 , H01L29/20 , H01L29/201 , H01L29/207 , H01L29/267 , H01L29/41783 , H01L29/4236 , H01L29/452 , H01L29/517 , H01L29/66522 , H01L29/66628 , H01L29/66636 , H01L29/66795 , H01L29/78 , H01L29/7827 , H01L29/7836 , H01L29/785 , H01L29/78603 , H01L29/78618 , H01L29/78681
摘要： A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.
摘要翻译： 描述具有窄带隙半导体源极/漏极区域的晶体管。 晶体管包括形成在形成于硅层上的栅介质层上的栅电极。 一对源极/漏极区域形成在栅电极的相对侧上，其中所述一对源极/漏极区域包括形成在栅电极的相对侧上的硅层中的窄带隙半导体膜。
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公开(公告)号：US08183556B2
公开(公告)日：2012-05-22
申请号：US11305452
申请日：2005-12-15
申请人： Suman Datt{dot over (a)} , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amlan , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau
发明人： Suman Datt{dot over (a)} , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amlan , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau
IPC分类号： H01L21/84
CPC分类号： H01L29/7784 , H01L21/02178 , H01L21/02381 , H01L21/02546 , H01L21/823807 , H01L21/823885 , H01L21/8252 , H01L27/0605 , H01L27/092 , H01L29/1054 , H01L29/122 , H01L29/15 , H01L29/157 , H01L29/205 , H01L29/41783 , H01L29/42364 , H01L29/42376 , H01L29/517 , H01L29/66462 , H01L29/66522 , H01L29/7783
摘要： A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.
摘要翻译： CMOS器件包括具有第一量子阱结构的PMOS晶体管和具有第二量子阱结构的NMOS器件。 PMOS和NMOS晶体管形成在衬底上。
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10.发明授权Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate 有权互补金属氧化物半导体集成电路使用升高源极漏极和替代金属栅极公开(公告)号：US08148786B2
公开(公告)日：2012-04-03
申请号：US12493291
申请日：2009-06-29
申请人： Jack Kavalieros , Annalisa Cappellani , Justin K. Brask , Mark L. Doczy , Matthew V. Metz , Suman Datta , Chris E. Barns , Robert S. Chau
发明人： Jack Kavalieros , Annalisa Cappellani , Justin K. Brask , Mark L. Doczy , Matthew V. Metz , Suman Datta , Chris E. Barns , Robert S. Chau
IPC分类号： H01L21/76
CPC分类号： H01L29/66636 , H01L21/28079 , H01L29/495 , H01L29/66545 , H01L29/7834
摘要： A complementary metal oxide semiconductor integrated circuit may be formed with a PMOS device formed using a replacement metal gate and a raised source drain. The raised source drain may be formed of epitaxially deposited silicon germanium material that is doped p-type. The replacement metal gate process results in a metal gate electrode and may involve the removal of a nitride etch stop layer.
摘要翻译： 互补金属氧化物半导体集成电路可以形成有使用替换金属栅极和升高源极漏极形成的PMOS器件。 凸起的源极漏极可以由掺杂p型的外延沉积的硅锗材料形成。 替代金属栅极工艺导致金属栅电极，并且可能涉及去除氮化物蚀刻停止层。
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