公开(公告)号：US08796133B2

公开(公告)日：2014-08-05

申请号：US13553941

申请日：2012-07-20

申请人： Griselda Bonilla ,  Timothy H. Daubenspeck ,  Mark C. H. Lamorey ,  Howard S. Landis ,  Xiao Hu Liu ,  David L. Questad ,  Thomas M. Shaw ,  David B. Stone

发明人： Griselda Bonilla ,  Timothy H. Daubenspeck ,  Mark C. H. Lamorey ,  Howard S. Landis ,  Xiao Hu Liu ,  David L. Questad ,  Thomas M. Shaw ,  David B. Stone

IPC分类号： H01L21/44 ,  H01L23/48

CPC分类号： H01L23/53295 ,  H01L23/3192 ,  H01L23/522 ,  H01L23/5329 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13021 ,  H01L2924/00014 ,  H01L2924/3512 ,  H01L2224/05552

摘要： A method of reducing white bump formation and dielectric cracking under controlled collapse chip connections (C4s). The method comprises fabricating a substrate having a plurality of metallization layers, one or more of the layers is of low k dielectric material. The substrate includes a plurality of attachment pads for the C4s. The fabricating comprises selectively forming at least a portion of the substrate with metal fill having a higher Young's modulus of elasticity than any of the one or more layers of low k dielectric material in portions of the substrate located beneath at least some of the attachment pads.

摘要翻译： 一种在受控的崩溃芯片连接（C4）下减少白色凸块形成和电介质裂纹的方法。 该方法包括制造具有多个金属化层的衬底，一个或多个层是低k电介质材料。 衬底包括用于C4的多个附接垫。 该制造包括在位于至少一些附接垫下方的衬底的部分中，选择性地形成具有比任何一种或多种低k电介质材料中的任何一种具有更高杨氏弹性模量的金属填充物的衬底的至少一部分。

公开(公告)号：US20140021622A1

公开(公告)日：2014-01-23

申请号：US13553941

申请日：2012-07-20

申请人： Griselda Bonilla ,  Timothy H. Daubenspeck ,  Mark C.H. Lamorey ,  Howard S. Landis ,  Xiao Hu Liu ,  David L. Questad ,  Thomas M. Shaw ,  David B. Stone

发明人： Griselda Bonilla ,  Timothy H. Daubenspeck ,  Mark C.H. Lamorey ,  Howard S. Landis ,  Xiao Hu Liu ,  David L. Questad ,  Thomas M. Shaw ,  David B. Stone

IPC分类号： H01L23/52 ,  H01L21/60

CPC分类号： H01L23/53295 ,  H01L23/3192 ,  H01L23/522 ,  H01L23/5329 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13021 ,  H01L2924/00014 ,  H01L2924/3512 ,  H01L2224/05552

摘要： A method of reducing white bump formation and dielectric cracking under controlled collapse chip connections (C4s). The method comprises fabricating a substrate having a plurality of metallization layers, one or more of the layers is of low k dielectric material. The substrate includes a plurality of attachment pads for the C4s. The fabricating comprises selectively forming at least a portion of the substrate with metal fill having a higher Young's modulus of elasticity than any of the one or more layers of low k dielectric material in portions of the substrate located beneath at least some of the attachment pads.

摘要翻译： 一种在受控的崩溃芯片连接（C4）下减少白色凸块形成和电介质裂纹的方法。 该方法包括制造具有多个金属化层的衬底，一个或多个层是低k电介质材料。 衬底包括用于C4的多个附接垫。 该制造包括在位于至少一些附接垫下方的衬底的部分中，选择性地形成具有比任何一种或多种低k电介质材料中的任何一种具有更高杨氏弹性模量的金属填充物的衬底的至少一部分。

公开(公告)号：US20080173985A1

公开(公告)日：2008-07-24

申请号：US11626552

申请日：2007-01-24

申请人： Michael P. Belyansky ,  Griselda Bonilla ,  Xiao Hu Liu ,  Son Van Nguyen ,  Thomas M. Shaw ,  Hosadurga K. Shobha ,  Daewon Yang

发明人： Michael P. Belyansky ,  Griselda Bonilla ,  Xiao Hu Liu ,  Son Van Nguyen ,  Thomas M. Shaw ,  Hosadurga K. Shobha ,  Daewon Yang

IPC分类号： H01L23/58 ,  H01L21/318

CPC分类号： H01L21/02123 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/318 ,  H01L21/3185 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76834

摘要： A dielectric cap and related methods are disclosed. In one embodiment, the dielectric cap includes a dielectric material having an optical band gap (e.g. greater than about 3.0 electron-Volts) to substantially block ultraviolet radiation during a curing treatment, and including nitrogen with electron donor, double bond electrons. The dielectric cap exhibits a high modulus and is stable under post ULK UV curing treatments for, for example: copper low k back-end-of-line (BEOL) nanoelectronic devices, leading to less film and device cracking and improved reliability,

摘要翻译： 公开了介电盖和相关方法。 在一个实施例中，电介质盖包括具有光学带隙（例如大于约3.0电子伏特）的电介质材料，以在固化处理期间基本上阻挡紫外线辐射，并且包括氮与电子给体，双键电子。 电介质盖表现出高模量，并且在ULK UV固化处理后稳定，例如：铜低k后端（BEOL）纳米电子器件，导致更少的膜和器件开裂和改善的可靠性，

公开(公告)号：US09006739B2

公开(公告)日：2015-04-14

申请号：US13448775

申请日：2012-04-17

申请人： James V. Crain, Jr. ,  Mark C. H. Lamorey ,  Christopher D. Muzzy ,  Thomas M. Shaw ,  David B. Stone

发明人： James V. Crain, Jr. ,  Mark C. H. Lamorey ,  Christopher D. Muzzy ,  Thomas M. Shaw ,  David B. Stone

IPC分类号： H01L21/66 ,  H01L23/522 ,  H01L23/00

CPC分类号： H01L22/34 ,  G01R31/2601 ,  G01R31/2607 ,  H01L23/522 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/13111 ,  H01L2224/14131 ,  H01L2224/14515 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/14

摘要： A method of testing an integrated circuit (IC) chip and a related test structure are disclosed. A test structure includes a monitor chain proximate to at least one solder bump pad, the monitor chain including at least one metal via stack, each metal via stack extending from a lower metal layer in the IC chip to an upper metal layer in the IC chip, such that the monitor chain forms a continuous circuit proximate to the at least one solder bump pad, and where each metal via stack is positioned substantially under the solder bump. A method for testing to detect boundaries of safe effective modulus includes performing a stress test on an IC chip containing the test structure joined to a semiconductor package.

公开(公告)号：US20130270558A1

公开(公告)日：2013-10-17

申请号：US13448775

申请日：2012-04-17

申请人： James V. Crain, JR. ,  Mark C. H. Lamorey ,  Christopher D. Muzzy ,  Thomas M. Shaw ,  David B. Stone

发明人： James V. Crain, JR. ,  Mark C. H. Lamorey ,  Christopher D. Muzzy ,  Thomas M. Shaw ,  David B. Stone

IPC分类号： H01L23/498 ,  H01L21/66

CPC分类号： H01L22/34 ,  G01R31/2601 ,  G01R31/2607 ,  H01L23/522 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/13111 ,  H01L2224/14131 ,  H01L2224/14515 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/14

摘要： A method of testing an integrated circuit (IC) chip and a related test structure are disclosed. A test structure includes a monitor chain proximate to at least one solder bump pad, the monitor chain including at least one metal via stack, each metal via stack extending from a lower metal layer in the IC chip to an upper metal layer in the IC chip, such that the monitor chain forms a continuous circuit proximate to the at least one solder bump pad, and where each metal via stack is positioned substantially under the solder bump. A method for testing to detect boundaries of safe effective modulus includes performing a stress test on an IC chip containing the test structure joined to a semiconductor package.

公开(公告)号：US20140024146A1

公开(公告)日：2014-01-23

申请号：US13565848

申请日：2012-08-03

申请人： Diego Anzola ,  Evan G. Colgan ,  Kevin K. Dezfulian ,  Daniel C. Edelstein ,  Mark C. H. Lamorey ,  Sampath Purushothaman ,  Thomas M. Shaw ,  Roy R. Yu

发明人： Diego Anzola ,  Evan G. Colgan ,  Kevin K. Dezfulian ,  Daniel C. Edelstein ,  Mark C. H. Lamorey ,  Sampath Purushothaman ,  Thomas M. Shaw ,  Roy R. Yu

IPC分类号： H01L21/768 ,  H01L21/50 ,  H01L21/66

CPC分类号： H01L23/585 ,  H01L23/562 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2225/06551 ,  H01L2225/06565

摘要： A semiconductor structure is provided and includes a substrate having an edge surface and a device surface with a central area, a crack stop structure disposed on the device surface and a circuit structure including components disposed on the device surface in the central area and interconnects electrically coupled to the components. The interconnects are configured to extend from the central area to the edge surface while bridging over the crack stop structure.

公开(公告)号：US20140021616A1

公开(公告)日：2014-01-23

申请号：US13553559

申请日：2012-07-19

申请人： Diego Anzola ,  Evan G. Colgan ,  Kevin K. Dezfulian ,  Daniel C. Edelstein ,  Mark C. H. Lamorey ,  Sampath Purushothaman ,  Thomas M. Shaw ,  Roy R. Yu

发明人： Diego Anzola ,  Evan G. Colgan ,  Kevin K. Dezfulian ,  Daniel C. Edelstein ,  Mark C. H. Lamorey ,  Sampath Purushothaman ,  Thomas M. Shaw ,  Roy R. Yu

IPC分类号： H01L23/532 ,  H01L23/58

CPC分类号： H01L23/585 ,  H01L23/562 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2225/06551 ,  H01L2225/06565

摘要： A semiconductor structure is provided and includes a substrate having an edge surface and a device surface with a central area, a crack stop structure disposed on the device surface and a circuit structure including components disposed on the device surface in the central area and interconnects electrically coupled to the components. The interconnects are configured to extend from the central area to the edge surface while bridging over the crack stop structure.

摘要翻译： 提供半导体结构，并且包括具有边缘表面的基底和具有中心区域的器件表面，设置在器件表面上的裂纹阻挡结构以及包括设置在中心区域的器件表面上的部件的电路结构，并将电耦合 到组件。 互连构造成在桥接在裂纹停止结构上的同时从中心区域延伸到边缘表面。

公开(公告)号：US20130049207A1

公开(公告)日：2013-02-28

申请号：US13221698

申请日：2011-08-30

申请人： Eric G. Liniger ,  Griselda Bonilla ,  Pak Leung ,  Stephan A. Cohen ,  Stephen M. Gates ,  Thomas M. Shaw

发明人： Eric G. Liniger ,  Griselda Bonilla ,  Pak Leung ,  Stephan A. Cohen ,  Stephen M. Gates ,  Thomas M. Shaw

IPC分类号： H01L21/26 ,  H01L23/485 ,  H01L21/66

CPC分类号： H01L21/3105 ,  H01L21/76828 ,  H01L21/76829 ,  H01L22/14

摘要： A method of annealing a semiconductor and a semiconductor. The method of annealing including heating the semiconductor to a first temperature for a first period of time sufficient to remove physically-adsorbed water from the semiconductor and heating the semiconductor to a second temperature, the second temperature being greater than the first temperature, for a period of time sufficient to remove chemically-adsorbed water from the semiconductor. A semiconductor device including a plurality of metal conductors, and a dielectric including regions separating the plurality of metal conductors, the regions including an upper interface and a lower bulk region, the upper interface having a density greater than a density of the lower bulk region.

摘要翻译： 半导体和半导体退火的方法。 退火方法包括将半导体加热到第一温度第一时间段，足以从半导体去除物理吸附的水，并将半导体加热到第二温度，第二温度大于第一温度一段时间 足以从半导体去除化学吸附的水。 一种包括多个金属导体的半导体器件，以及包括分隔多个金属导体的区域的电介质，所述区域包括上界面和下体块区域，所述上界面的密度大于所述下体积区域的密度。

公开(公告)号：US09018089B2

公开(公告)日：2015-04-28

申请号：US13221698

申请日：2011-08-30

申请人： Eric G. Liniger ,  Griselda Bonilla ,  Pak Leung ,  Stephen A. Cohen ,  Stephen M. Gates ,  Thomas M. Shaw

发明人： Eric G. Liniger ,  Griselda Bonilla ,  Pak Leung ,  Stephen A. Cohen ,  Stephen M. Gates ,  Thomas M. Shaw

IPC分类号： H01L21/26 ,  H01L21/3105 ,  H01L21/66 ,  H01L21/768

CPC分类号： H01L21/3105 ,  H01L21/76828 ,  H01L21/76829 ,  H01L22/14

摘要： A method of annealing a semiconductor and a semiconductor. The method of annealing including heating the semiconductor to a first temperature for a first period of time sufficient to remove physically-adsorbed water from the semiconductor and heating the semiconductor to a second temperature, the second temperature being greater than the first temperature, for a period of time sufficient to remove chemically-adsorbed water from the semiconductor. A semiconductor device including a plurality of metal conductors, and a dielectric including regions separating the plurality of metal conductors, the regions including an upper interface and a lower bulk region, the upper interface having a density greater than a density of the lower bulk region.

摘要翻译： 半导体和半导体退火的方法。 退火方法包括将半导体加热到第一温度第一时间段，足以从半导体去除物理吸附的水，并将半导体加热到第二温度，第二温度大于第一温度一段时间 足以从半导体去除化学吸附的水。 一种包括多个金属导体的半导体器件，以及包括分隔多个金属导体的区域的电介质，所述区域包括上界面和下体块区域，所述上界面的密度大于所述下体积区域的密度。

公开(公告)号：US07847402B2

公开(公告)日：2010-12-07

申请号：US11676522

申请日：2007-02-20

申请人： Darryl D. Restaino ,  Griselda Bonilla ,  Christos D. Dimitrakopoulos ,  Stephen M. Gates ,  Jae H. Kim ,  Michael W. Lane ,  Xiao H. Liu ,  Son V. Nguyen ,  Thomas M. Shaw ,  Johnny Widodo

发明人： Darryl D. Restaino ,  Griselda Bonilla ,  Christos D. Dimitrakopoulos ,  Stephen M. Gates ,  Jae H. Kim ,  Michael W. Lane ,  Xiao H. Liu ,  Son V. Nguyen ,  Thomas M. Shaw ,  Johnny Widodo

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L23/53295 ,  H01L21/76822 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A chip is provided which includes a back-end-of-line (“BEOL”) interconnect structure. The BEOL interconnect structure includes a plurality of interlevel dielectric (“ILD”) layers which include a dielectric material curable by ultraviolet (“UV”) radiation. A plurality of metal interconnect wiring layers are embedded in the plurality of ILD layers. Dielectric barrier layers cover the plurality of metal interconnect wiring layers, the dielectric barrier layers being adapted to reduce diffusion of materials between the metal interconnect wiring layers and the ILD layers. One of more of the dielectric barrier layers is adapted to retain compressive stress while withstanding UV radiation sufficient to cure the dielectric material of the ILD layers, making the BEOL structure better capable of avoiding deformation due to thermal and/or mechanical stress.

摘要翻译： 提供了包括后端行（“BEOL”）互连结构的芯片。 BEOL互连结构包括多个层间电介质（“ILD”）层，其包括通过紫外线（“UV”）辐射固化的电介质材料。 多个金属互连配线层嵌入在多个ILD层中。 介电阻挡层覆盖多个金属互连布线层，介电阻挡层适于减少材料在金属互连布线层和ILD层之间的扩散。 介质阻挡层中的一个适于保持压缩应力，同时承受足以固化ILD层的介电材料的UV辐射，使得BEOL结构更好地能够避免由于热和/或机械应力引起的变形。