公开(公告)号：US20140021622A1

公开(公告)日：2014-01-23

申请号：US13553941

申请日：2012-07-20

申请人： Griselda Bonilla ,  Timothy H. Daubenspeck ,  Mark C.H. Lamorey ,  Howard S. Landis ,  Xiao Hu Liu ,  David L. Questad ,  Thomas M. Shaw ,  David B. Stone

发明人： Griselda Bonilla ,  Timothy H. Daubenspeck ,  Mark C.H. Lamorey ,  Howard S. Landis ,  Xiao Hu Liu ,  David L. Questad ,  Thomas M. Shaw ,  David B. Stone

IPC分类号： H01L23/52 ,  H01L21/60

CPC分类号： H01L23/53295 ,  H01L23/3192 ,  H01L23/522 ,  H01L23/5329 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13021 ,  H01L2924/00014 ,  H01L2924/3512 ,  H01L2224/05552

摘要： A method of reducing white bump formation and dielectric cracking under controlled collapse chip connections (C4s). The method comprises fabricating a substrate having a plurality of metallization layers, one or more of the layers is of low k dielectric material. The substrate includes a plurality of attachment pads for the C4s. The fabricating comprises selectively forming at least a portion of the substrate with metal fill having a higher Young's modulus of elasticity than any of the one or more layers of low k dielectric material in portions of the substrate located beneath at least some of the attachment pads.

摘要翻译： 一种在受控的崩溃芯片连接（C4）下减少白色凸块形成和电介质裂纹的方法。 该方法包括制造具有多个金属化层的衬底，一个或多个层是低k电介质材料。 衬底包括用于C4的多个附接垫。 该制造包括在位于至少一些附接垫下方的衬底的部分中，选择性地形成具有比任何一种或多种低k电介质材料中的任何一种具有更高杨氏弹性模量的金属填充物的衬底的至少一部分。

公开(公告)号：US08796133B2

公开(公告)日：2014-08-05

申请号：US13553941

申请日：2012-07-20

申请人： Griselda Bonilla ,  Timothy H. Daubenspeck ,  Mark C. H. Lamorey ,  Howard S. Landis ,  Xiao Hu Liu ,  David L. Questad ,  Thomas M. Shaw ,  David B. Stone

发明人： Griselda Bonilla ,  Timothy H. Daubenspeck ,  Mark C. H. Lamorey ,  Howard S. Landis ,  Xiao Hu Liu ,  David L. Questad ,  Thomas M. Shaw ,  David B. Stone

IPC分类号： H01L21/44 ,  H01L23/48

CPC分类号： H01L23/53295 ,  H01L23/3192 ,  H01L23/522 ,  H01L23/5329 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13021 ,  H01L2924/00014 ,  H01L2924/3512 ,  H01L2224/05552

摘要： A method of reducing white bump formation and dielectric cracking under controlled collapse chip connections (C4s). The method comprises fabricating a substrate having a plurality of metallization layers, one or more of the layers is of low k dielectric material. The substrate includes a plurality of attachment pads for the C4s. The fabricating comprises selectively forming at least a portion of the substrate with metal fill having a higher Young's modulus of elasticity than any of the one or more layers of low k dielectric material in portions of the substrate located beneath at least some of the attachment pads.

摘要翻译： 一种在受控的崩溃芯片连接（C4）下减少白色凸块形成和电介质裂纹的方法。 该方法包括制造具有多个金属化层的衬底，一个或多个层是低k电介质材料。 衬底包括用于C4的多个附接垫。 该制造包括在位于至少一些附接垫下方的衬底的部分中，选择性地形成具有比任何一种或多种低k电介质材料中的任何一种具有更高杨氏弹性模量的金属填充物的衬底的至少一部分。

公开(公告)号：US20080173985A1

公开(公告)日：2008-07-24

申请号：US11626552

申请日：2007-01-24

申请人： Michael P. Belyansky ,  Griselda Bonilla ,  Xiao Hu Liu ,  Son Van Nguyen ,  Thomas M. Shaw ,  Hosadurga K. Shobha ,  Daewon Yang

发明人： Michael P. Belyansky ,  Griselda Bonilla ,  Xiao Hu Liu ,  Son Van Nguyen ,  Thomas M. Shaw ,  Hosadurga K. Shobha ,  Daewon Yang

IPC分类号： H01L23/58 ,  H01L21/318

CPC分类号： H01L21/02123 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/318 ,  H01L21/3185 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76834

摘要： A dielectric cap and related methods are disclosed. In one embodiment, the dielectric cap includes a dielectric material having an optical band gap (e.g. greater than about 3.0 electron-Volts) to substantially block ultraviolet radiation during a curing treatment, and including nitrogen with electron donor, double bond electrons. The dielectric cap exhibits a high modulus and is stable under post ULK UV curing treatments for, for example: copper low k back-end-of-line (BEOL) nanoelectronic devices, leading to less film and device cracking and improved reliability,

摘要翻译： 公开了介电盖和相关方法。 在一个实施例中，电介质盖包括具有光学带隙（例如大于约3.0电子伏特）的电介质材料，以在固化处理期间基本上阻挡紫外线辐射，并且包括氮与电子给体，双键电子。 电介质盖表现出高模量，并且在ULK UV固化处理后稳定，例如：铜低k后端（BEOL）纳米电子器件，导致更少的膜和器件开裂和改善的可靠性，

公开(公告)号：US08076756B2

公开(公告)日：2011-12-13

申请号：US13031195

申请日：2011-02-19

申请人： Michael W. Lane ,  Xiao Hu Liu ,  Thomas M. Shaw ,  Mukta G. Farooq ,  Robert Hannon ,  Ian D. W. Melville

发明人： Michael W. Lane ,  Xiao Hu Liu ,  Thomas M. Shaw ,  Mukta G. Farooq ,  Robert Hannon ,  Ian D. W. Melville

IPC分类号： H01L23/544

CPC分类号： H01L29/0657 ,  H01L21/563 ,  H01L21/78 ,  H01L23/5329 ,  H01L23/562 ,  H01L23/585 ,  H01L24/90 ,  H01L2224/73203 ,  H01L2224/90 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/18301 ,  H01L2924/00

摘要： A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT.

摘要翻译： 半导体产品包括具有顶表面和包括半导体芯片的底表面的半导体衬底。 半导体衬底具有顶表面和周边。 在周边的芯片中形成屏障。 在深度隔离沟槽（UDIT）中切割在芯片的上表面，其在周边和屏障之间向下延伸。 在形成屏障和UDIT之前，在衬底上形成具有低k pSICOH电介质和硬掩模层的ILD结构。 除了UDIT之外，ILD结构互连结构可以向下凹入底层。

公开(公告)号：US06972209B2

公开(公告)日：2005-12-06

申请号：US10306534

申请日：2002-11-27

申请人： Birendra N. Agarwala ,  Conrad A. Barile ,  Hormazdyar M. Dalal ,  Brett H. Engle ,  Michael Lane ,  Ernest Levine ,  Xiao Hu Liu ,  Vincent McGahay ,  John F. McGrath ,  Conal E. Murray ,  Jawahar P. Nayak ,  Du B. Nguyen ,  Hazara S. Rathore ,  Thomas M. Shaw

发明人： Birendra N. Agarwala ,  Conrad A. Barile ,  Hormazdyar M. Dalal ,  Brett H. Engle ,  Michael Lane ,  Ernest Levine ,  Xiao Hu Liu ,  Vincent McGahay ,  John F. McGrath ,  Conal E. Murray ,  Jawahar P. Nayak ,  Du B. Nguyen ,  Hazara S. Rathore ,  Thomas M. Shaw

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/00

CPC分类号： H01L23/53295 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76838 ,  H01L23/5226 ,  H01L2924/0002 ,  Y10T428/24917 ,  H01L2924/00

摘要： A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material. The dielectric layer of each of the multiple interconnection levels includes a soft low-k dielectric material, wherein the cantilever and set of stacked via-studs are integrated within the soft low-k dielectric material to increase resistance to thermal fatigue crack formation. In one embodiment, each of the set of stacked via-studs in the low-k dielectric material layers is provided with a cantilever, such that the cantilevers are interwoven by connecting a cantilever on one level to a bulk portion of the conductor line on adjacent levels of interconnection, thereby increasing flexibility of stacked via-studs between interconnection levels.

摘要翻译： 一种多级半导体集成电路（IC）结构，包括在半导体衬底上包括电介质材料层的第一互连电平，所述介电材料层包括用于钝化半导体器件的致密材料和其下的局部互连; 形成在致密电介质材料层之上的电介质材料的多个互连层，每层介电材料包括至少一层低k电介质材料; 以及在低k电介质材料层中的一组堆叠的通孔螺钉，每组所述一组堆叠通孔柱互连一个或多个图案化导电结构，包括形成在低k电介质材料中的悬臂的导电结构。 多个互连级别中的每一个的电介质层包括软的低k电介质材料，其中悬臂和一组堆叠的通孔螺钉集成在软低k电介质材料内，以增加对热疲劳裂纹形成的抵抗力。 在一个实施例中，低k电介质材料层中的每组叠置通孔螺柱设置有悬臂，使得悬臂通过将一个级上的悬臂连接到相邻的导体线的主体部分而交织 互连级别，从而增加互连级别之间堆叠通孔的灵活性。

公开(公告)号：US20110140245A1

公开(公告)日：2011-06-16

申请号：US13031195

申请日：2011-02-19

申请人： MICHAEL W. LANE ,  Xiao Hu Liu ,  Thomas M. Shaw ,  Mukta G. Farooq ,  Robert Hannon ,  Ian D.W. Melville

发明人： MICHAEL W. LANE ,  Xiao Hu Liu ,  Thomas M. Shaw ,  Mukta G. Farooq ,  Robert Hannon ,  Ian D.W. Melville

IPC分类号： H01L23/58

CPC分类号： H01L29/0657 ,  H01L21/563 ,  H01L21/78 ,  H01L23/5329 ,  H01L23/562 ,  H01L23/585 ,  H01L24/90 ,  H01L2224/73203 ,  H01L2224/90 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/18301 ,  H01L2924/00

摘要： A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT.

摘要翻译： 半导体产品包括具有顶表面和包括半导体芯片的底表面的半导体衬底。 半导体衬底具有顶表面和周边。 在周边的芯片中形成屏障。 在深度隔离沟槽（UDIT）中切割在芯片的上表面，其在周边和屏障之间向下延伸。 在形成屏障和UDIT之前，在衬底上形成具有低k pSICOH电介质和硬掩模层的ILD结构。 除了UDIT之外，ILD结构互连结构可以向下凹入底层。

公开(公告)号：US07955955B2

公开(公告)日：2011-06-07

申请号：US11746684

申请日：2007-05-10

申请人： Michael W. Lane ,  Xiao Hu Liu ,  Thomas M. Shaw ,  Mukta G. Farooq ,  Robert Hannon ,  Ian D. W. Melville

发明人： Michael W. Lane ,  Xiao Hu Liu ,  Thomas M. Shaw ,  Mukta G. Farooq ,  Robert Hannon ,  Ian D. W. Melville

IPC分类号： H01L21/301

CPC分类号： H01L29/0657 ,  H01L21/563 ,  H01L21/78 ,  H01L23/5329 ,  H01L23/562 ,  H01L23/585 ,  H01L24/90 ,  H01L2224/73203 ,  H01L2224/90 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/18301 ,  H01L2924/00

摘要： A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT.

摘要翻译： 半导体产品包括具有顶表面和包括半导体芯片的底表面的半导体衬底。 半导体衬底具有顶表面和周边。 在周边的芯片中形成屏障。 在深度隔离沟槽（UDIT）中切割在芯片的上表面，其在周边和屏障之间向下延伸。 在形成屏障和UDIT之前，在衬底上形成具有低k pSICOH电介质和硬掩模层的ILD结构。 除了UDIT之外，ILD结构互连结构可以向下凹入底层。

公开(公告)号：US20080277765A1

公开(公告)日：2008-11-13

申请号：US11746684

申请日：2007-05-10

申请人： Michael W. Lane ,  Xiao Hu Liu ,  Thomas M. Shaw ,  Mukta G. Farooq ,  Robert Hannon ,  Ian D. W. Melville

发明人： Michael W. Lane ,  Xiao Hu Liu ,  Thomas M. Shaw ,  Mukta G. Farooq ,  Robert Hannon ,  Ian D. W. Melville

IPC分类号： H01L21/78 ,  H01L29/06

CPC分类号： H01L29/0657 ,  H01L21/563 ,  H01L21/78 ,  H01L23/5329 ,  H01L23/562 ,  H01L23/585 ,  H01L24/90 ,  H01L2224/73203 ,  H01L2224/90 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/18301 ,  H01L2924/00

摘要： A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT.

摘要翻译： 半导体产品包括具有顶表面和包括半导体芯片的底表面的半导体衬底。 半导体衬底具有顶表面和周边。 在周边的芯片中形成屏障。 在深度隔离沟槽（UDIT）中切割在芯片的上表面，其在周边和屏障之间向下延伸。 在形成屏障和UDIT之前，在衬底上形成具有低k pSICOH电介质和硬掩模层的ILD结构。 除了UDIT之外，ILD结构互连结构可以向下凹入底层。

公开(公告)号：US07260810B2

公开(公告)日：2007-08-21

申请号：US10687475

申请日：2003-10-16

申请人： Ronald G. Filippi, Jr. ,  Giovanni Fiorenza ,  Xiao Hu Liu ,  Conal Eugene Murray ,  Gregory Allen Northrop ,  Thomas M. Shaw ,  Richard Andre′ Wachnik ,  Mary Yvonne Lanzerotti Wisniewski

发明人： Ronald G. Filippi, Jr. ,  Giovanni Fiorenza ,  Xiao Hu Liu ,  Conal Eugene Murray ,  Gregory Allen Northrop ,  Thomas M. Shaw ,  Richard Andre′ Wachnik ,  Mary Yvonne Lanzerotti Wisniewski

IPC分类号： G06F17/50 ,  G03F1/00

CPC分类号： G06F17/5018

摘要： A method for analyzing circuit designs includes discretizing a design representation into pixel elements representative of a structure in the design and determining at least one property for each pixel element representing a portion of the design. Then, a response of the design is determined due to local properties across the design.

摘要翻译： 用于分析电路设计的方法包括将设计表示离散成代表设计中的结构的像素元素，并且为表示设计的一部分的每个像素元素确定至少一个属性。 然后，由于设计中的局部属性，确定了设计的响应。

公开(公告)号：US08604618B2

公开(公告)日：2013-12-10

申请号：US13239533

申请日：2011-09-22

申请人： Edward C. Cooney, III ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Xiao Hu Liu ,  Thomas L. McDevitt ,  Gary L. Milo ,  William J. Murphy

发明人： Edward C. Cooney, III ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Xiao Hu Liu ,  Thomas L. McDevitt ,  Gary L. Milo ,  William J. Murphy

IPC分类号： H01L23/485 ,  H01L21/3205

CPC分类号： H01L21/76802 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53295 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and a method of fabricating the same, includes vertically stacked layers on an insulator. Each of the layers includes a first dielectric insulator portion, a first metal conductor embedded within the first dielectric insulator portion, a first nitride cap covering the first metal conductor, a second dielectric insulator portion, a second metal conductor embedded within the second dielectric insulator portion, and a second nitride cap covering the second metal conductor. The first and second metal conductors form first vertically stacked conductor layers and second vertically stacked conductor layers. The first vertically stacked conductor layers are proximate the second vertically stacked conductor layers, and at least one air gap is positioned between the first vertically stacked conductor layers and the second vertically stacked conductor layers. An upper semiconductor layer covers the first vertically stacked conductor layers, the air gap and the second plurality of vertically stacked conductor layers.

摘要翻译： 半导体器件及其制造方法包括在绝缘体上的垂直堆叠的层。 每个层包括第一介电绝缘体部分，嵌入在第一介电绝缘体部分内的第一金属导体，覆盖第一金属导体的第一氮化物帽，第二电介质绝缘体部分，嵌入在第二介电绝缘体部分内的第二金属导体 以及覆盖所述第二金属导体的第二氮化物帽。 第一和第二金属导体形成第一垂直堆叠的导体层和第二垂直堆叠的导体层。 第一垂直堆叠的导体层靠近第二垂直堆叠的导体层，并且至少一个气隙位于第一垂直堆叠的导体层和第二垂直堆叠的导体层之间。 上半导体层覆盖第一垂直堆叠的导体层，气隙和第二多个垂直堆叠的导体层。