公开(公告)号：US5397748A

公开(公告)日：1995-03-14

申请号：US996978

申请日：1992-12-24

申请人： Hirohito Watanabe ,  Sadayuki Ohnishi

发明人： Hirohito Watanabe ,  Sadayuki Ohnishi

IPC分类号： H01L21/02 ,  H01L21/314 ,  H01L21/321

CPC分类号： H01L28/40 ,  H01L21/3145 ,  H01L21/32105 ,  H01L21/3211 ,  Y10S148/014

摘要： A thermal oxidation method for producing a semiconductor device having a capacitor insulating film structure capable of making a thin film having a small leakage current and small temperature dependence of the leakage current. In the insulating film, a silicon nitride film with a small electron mobility and a silicon oxide film with a small hole mobility are alternately laminated in order of the nitride film/oxide film/nitride film/oxide film from a lower electrode side. A current component such as electrons flowing in this insulating film structure is limited by the layer with the smaller mobility to reduce the leakage current. An oxide film thickness of approximately several .ANG. can thus be strictly controlled. By forming the silicon nitride film between the high dielectric oxide film and the electrode, the reaction of the silicon electrode and the high dielectric oxide film can be prevented.

摘要翻译： 一种用于制造具有能够制造具有小泄漏电流和较小的漏电流的温度依赖性的薄膜的电容器绝缘膜结构的半导体器件的热氧化方法。 在绝缘膜中，具有小电子迁移率的氮化硅膜和具有小空穴迁移率的氧化硅膜按照来自下电极侧的氮化物膜/氧化膜/氮化物膜/氧化物膜的顺序交替层叠。 在该绝缘膜结构中流动的电子的电流成分被具有较小迁移率的层限制，以减少漏电流。 因此可以严格控制大约几个ANGSTROM的氧化膜厚度。 通过在高电介质氧化膜和电极之间形成氮化硅膜，可以防止硅电极和高电介质氧化膜的反应。

公开(公告)号：US09247651B2

公开(公告)日：2016-01-26

申请号：US12754929

申请日：2010-04-06

申请人： Hirohito Watanabe

发明人： Hirohito Watanabe

IPC分类号： H05K1/00 ,  H05K1/03 ,  H05K1/16 ,  H05K1/11 ,  H05K3/28 ,  H05K1/02 ,  H05K3/00 ,  H05K3/38

CPC分类号： H05K3/281 ,  H05K1/0281 ,  H05K3/0058 ,  H05K3/386 ,  H05K2201/2009 ,  H05K2203/0195 ,  H05K2203/0278 ,  Y10T29/49124

摘要： To improve reliability by preventing separation of a sheet material attached on a flexible printed circuit, provided is a flexible printed circuit including a printed board body and a reinforcing board. A leaked portion of an adhesive agent is formed to leak in an outward direction relative to an end surface of the reinforcing board. The leaked portion adheres to part of the end surface of the reinforcing board to be continuous from a lower end of the end surface to form an inclined surface tapered in the outward direction. The leaked portion is formed such that a portion thereof that covers the end surface has an adhesion height hA, as measured from an adhesive surface of the reinforcing board, of greater than 0% and not greater than 80% of the thickness H1 of the reinforcing board.

摘要翻译： 为了通过防止附着在柔性印刷电路上的片材的分离来提高可靠性，提供了包括印刷板主体和加强板的柔性印刷电路。 粘合剂的泄漏部形成为相对于加强板的端面在向外方向泄漏。 泄漏部分粘附在加强板的端面的一部分上，从端面的下端连续，形成向外方向倾斜的倾斜面。 泄漏部分形成为使得其覆盖端面的部分具有从加强板的粘合表面测量的粘合高度hA大于加强件的厚度H1的0％且不大于80％ 板。

公开(公告)号：US09006579B2

公开(公告)日：2015-04-14

申请号：US13617366

申请日：2012-09-14

申请人： Masatoshi Inaba ,  Hiroshi Miyata ,  Hirohito Watanabe

发明人： Masatoshi Inaba ,  Hiroshi Miyata ,  Hirohito Watanabe

IPC分类号： B32B38/10 ,  H05K1/00 ,  H05K3/24 ,  H05K3/26 ,  H05K1/11

CPC分类号： H05K3/244 ,  H05K1/118 ,  H05K3/26

摘要： A method of manufacturing a printed circuit board includes: forming a copper layer of an interconnection pattern on a base film; laminating a cover lay on the base film so as to expose a part of the copper layer from the cover lay and cover the copper layer by the cover lay; mechanically polishing at least the exposed portion of the copper layer; and performing a plating process on the exposed portion of the copper layer so as to form a plated layer on the copper layer, and the angles α1 and α2 between the polishing direction of the exposed portion of the copper layer and the bending lines C1 and C2 satisfy the following formula (1): 30°≦α1 and α2≦150°  (1).

摘要翻译： 制造印刷电路板的方法包括：在基膜上形成互连图形的铜层; 将盖层叠在基膜上，以便从覆盖层露出铜层的一部分，并通过覆盖层覆盖铜层; 至少机械抛光铜层的暴露部分; 对铜层的露出部进行电镀处理，在铜层上形成镀层，铜层的露出部的研磨方向和弯曲线C1，C2的角度α1，α2 满足下列公式（1）：30°＆nlE;α1和α2＆nlE; 150°（1）。

公开(公告)号：US08177561B2

公开(公告)日：2012-05-15

申请号：US12302867

申请日：2007-05-23

申请人： Yasuhiro Ouchi ,  Shinichi Nikaido ,  Haruo Miyazawa ,  Hirohito Watanabe ,  Katsuya Yamagami

发明人： Yasuhiro Ouchi ,  Shinichi Nikaido ,  Haruo Miyazawa ,  Hirohito Watanabe ,  Katsuya Yamagami

IPC分类号： H05K1/00

CPC分类号： H05K7/1069 ,  H01L2924/3511 ,  H01R12/52 ,  H01R12/714 ,  H01R13/2485 ,  Y10T29/53209

摘要： A socket contact terminal for electrical connection between a connection portion formed of a metal conductor on a printed circuit board and a connection terminal of an IC package. The contact terminal comprises a metal terminal composed of a main columnar portion and arm portions on both sides and having an angular U shape and an elastomeric member attached to the metal terminal. A metal surface is exposed from the outer surface of each arm portion. The elastomeric member is firmly held between the arm portions of the metal terminal and exhibits a repulsive force when the arm portions are pressed in the direction that the arm portions approach each other.

摘要翻译： 一种插座接触端子，用于在由印刷电路板上的金属导体形成的连接部分和IC封装的连接端子之间进行电连接。 接触端子包括由主柱状部分和两侧的臂部分组成的并具有角度U形的金属端子和附接到金属端子的弹性体部件。 金属表面从每个臂部分的外表面露出。 弹性构件牢固地保持在金属端子的臂部之间，并且当臂部沿着臂部彼此接近的方向被按压时呈现排斥力。

公开(公告)号：US20080144377A1

公开(公告)日：2008-06-19

申请号：US11667736

申请日：2005-11-16

申请人： Hirohito Watanabe ,  Motofumi Saitou ,  Hiroshi Sunamura

发明人： Hirohito Watanabe ,  Motofumi Saitou ,  Hiroshi Sunamura

IPC分类号： G11C16/00 ,  H01L21/8247 ,  H01L29/788

CPC分类号： H01L27/11534 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/10 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L29/42324 ,  H01L29/66825

摘要： A diffusion layer (102) is formed in the surface region of a semiconductor substrate (101). A control gate electrode (103) is formed on the substrate. An interlayer dielectric film (108) covers the entire surface of the substrate. A drain leader line (104) made of a semiconductor such as n-type polysilicon is led from the drain region, and a source leader line (107) is led from the source region through the interlayer dielectric film. The drain leader line is surrounded by an annular floating gate (105). In erase, for example, the control gate is set to a ground potential, and a positive voltage is applied to the drain leader line to remove electrons in the floating gate to the drain leader line. In write, positive voltages are applied to the control gate electrode and drain leader line to generate CHE and inject hot electrons into the floating gate. This allows to thin the gate insulating film of a flash memory, increase the degree of integration of a nonvolatile memory, and lower the driving voltage.

摘要翻译： 在半导体衬底（101）的表面区域形成扩散层（102）。 在基板上形成控制栅电极（103）。 层间绝缘膜（108）覆盖基板的整个表面。 由漏极区域引出由诸如n型多晶硅的半导体制成的漏极引线（104），并且源极引线（107）从源极区域通过层间绝缘膜引出。 排水引导线被环形浮动门（105）包围。 在擦除中，例如，将控制栅极设置为接地电位，并且将正电压施加到漏极引线，以将浮动栅极中的电子去除到漏极引线。 在写入时，正电压施加到控制栅电极和漏极引线，以产生CHE并将热电子注入浮栅。 这样可以使闪存的栅极绝缘膜变薄，增加非易失性存储器的集成度，并降低驱动电压。

公开(公告)号：US07238996B2

公开(公告)日：2007-07-03

申请号：US11129439

申请日：2005-05-16

申请人： Naohiko Kimizuka ,  Kiyotaka Imai ,  Yuri Masuoka ,  Toshiyuki Iwamoto ,  Motofumi Saitoh ,  Hirohito Watanabe ,  Ayuka Tada

发明人： Naohiko Kimizuka ,  Kiyotaka Imai ,  Yuri Masuoka ,  Toshiyuki Iwamoto ,  Motofumi Saitoh ,  Hirohito Watanabe ,  Ayuka Tada

IPC分类号： H01L29/70

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/31155 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/517

摘要： A semiconductor device 100 comprises a silicon substrate 102, an N-type MOSFET 118 including a high concentration-high dielectric constant film 108b formed on the silicon substrate 102 and a polycrystalline silicon film 114, and a P-type MOSFET 120 including a low concentration-high dielectric constant film 108a and a polycrystalline silicon film 114 formed on the semiconductor substrate 102 to be juxtaposed to the N-type MOSFET 118. The low concentration-high dielectric constant film 108a and the high concentration-high dielectric constant film 108b are composed of a material containing one or more element (s) selected from a group consisting of Hf and Zr. The concentration of the above-described metallic element contained in the low concentration-high dielectric constant film 108a is lower than that contained in the high concentration-high dielectric constant film 108b.

摘要翻译： 半导体器件100包括硅衬底102，包括形成在硅衬底102上的高浓度 - 高介电常数膜108b和多晶硅膜114的N型MOSFET 118以及包括低电平的P型MOSFET 120 浓度高介电常数膜108a和形成在半导体衬底102上并与N型MOSFET 118并置的多晶硅膜114。 低浓度 - 高介电常数膜108a和高浓度 - 高介电常数膜108b由含有选自Hf和Zr的一种或多种元素的材料构成。 包含在低浓度 - 高介电常数膜108a中的上述金属元素的浓度低于高浓度 - 高介电常数膜108b中包含的金属元素的浓度。

公开(公告)号：US20060131670A1

公开(公告)日：2006-06-22

申请号：US10561608

申请日：2004-04-26

申请人： Takashi Ogura ,  Nobuyuki Ikarashi ,  Toshiyuki Iwamoto ,  Hirohito Watanabe

发明人： Takashi Ogura ,  Nobuyuki Ikarashi ,  Toshiyuki Iwamoto ,  Hirohito Watanabe

IPC分类号： H01L29/76

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28211 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/78

摘要： A semiconductor device provided with a MIS type field effect transistor comprising a silicon substrate, a gate insulating film having a high-dielectric-constant metal oxide film which is formed on the silicon substrate via a silicon containing insulating film, a silicon-containing gate electrode formed on the gate insulating film, and a sidewall including, as a constituting material, silicon oxide on a lateral face side of the gate electrode, wherein a silicon nitride film is interposed between the sidewall and at least the lateral face of the gate electrode. This semiconductor device, although having a fine structure with a small gate length, is capable of low power consumption and fast operation.

摘要翻译： 一种设置有MIS型场效应晶体管的半导体器件，包括硅衬底，具有通过含硅绝缘膜形成在硅衬底上的高介电常数金属氧化物膜的栅极绝缘膜，含硅栅电极 形成在所述栅极绝缘膜上的侧壁，以及在所述栅电极的侧面上包含氧化硅作为构成材料的侧壁，其中，所述侧壁与所述栅电极的至少所述侧面之间插入有氮化硅膜。 该半导体器件尽管具有栅极长度小的精细结构，但能够实现低功耗和快速操作。

公开(公告)号：US6140204A

公开(公告)日：2000-10-31

申请号：US118931

申请日：1998-07-20

申请人： Hirohito Watanabe

发明人： Hirohito Watanabe

IPC分类号： H01L27/04 ,  C23C16/24 ,  C23C16/44 ,  H01L21/02 ,  H01L21/205 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/20

CPC分类号： H01L28/84 ,  C23C16/24 ,  C23C16/44

摘要： Ingredient gas is first supplied into a reacting section disposed in an apparatus for chemical vapor deposition. Subsequently, a silicon film is deposited on a wafer under a condition that temperature at the upstream side of a direction of the ingredient gas flow inside the reacting section is higher than that at the downstream side thereof.

摘要翻译： 首先将成分气体供给到设置在化学气相沉积装置中的反应部分中。 随后，在反应部分内的成分气体流动方向的上游侧的温度高于其下游侧的温度的条件下，在晶片上沉积硅膜。

公开(公告)号：US6022772A

公开(公告)日：2000-02-08

申请号：US966543

申请日：1997-11-10

申请人： Hirohito Watanabe ,  Ichiroh Honma

发明人： Hirohito Watanabe ,  Ichiroh Honma

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  H01L21/8234

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： In a semiconductor device, such as a memory cell, including a capacitor, a corrugated electrode is used as a lower electrode of the capacitor and is covered with an insulation film to be opposed to an upper electrode. The corrugated electrode is specified in section by a series of folded portions which are alternately folded vertically and horizontally. Practically, the corrugated electrode is formed by a corrugated wall which surrounds a hollow space and which has a rectangular or a polygonal shape on a plane. Alternatively, the corrugated wall has an irregular surface formed by an aggregation of grains so as to effectively widen a surface of the lower electrode. Such a corrugated electrode may be manufactured by a mold which is formed by selectively etching a stack of first-kind spacer films and second-kind spacer films.

摘要翻译： 在诸如包括电容器的存储单元的半导体器件中，使用波纹状电极作为电容器的下电极，并且被绝缘膜覆盖以与上电极相对。 波纹状电极通过垂直和水平交替折叠的一系列折叠部分来界定。 实际上，波纹状电极由围绕中空空间的波纹壁形成，并且在平面上具有矩形或多边形。 或者，波纹状壁具有由晶粒聚集形成的不规则表面，以有效地加宽下电极的表面。 这种波纹状电极可以通过通过选择性地蚀刻第一种间隔膜和第二种间隔膜的堆叠形成的模具来制造。

公开(公告)号：US5658417A

公开(公告)日：1997-08-19

申请号：US447557

申请日：1995-05-23

申请人： Hirohito Watanabe ,  Mitsusuke Kyogoku

发明人： Hirohito Watanabe ,  Mitsusuke Kyogoku

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/306

CPC分类号： H01L21/31116

摘要： In order to study an etching rate difference of a layer formed mainly with silicon dioxide on a wafer, a thermal oxide film (113) and layers of BSG (117), BPSG (125), and PSG (129) are laminated on a wafer and are etched in a gaseous etching atmosphere consisting essentially of hydrogen fluoride or a mixture of hydrogen fluoride and water vapor. The layers are etched with various etching rates which are higher than that of the thermal oxide film. The etching rate difference is a difference between the etching rate of each layer and an etching rate of the thermal oxide film. The layers may include impurities, such as boron and phosphorus, collectively as a part of a layer material of each layer. The etching rate difference depends on the layer material. Preferably, the gaseous etching atmosphere should have a reduced pressure. Alternatively, a water vapor partial pressure should not be greater than 2000 Pa. As a further alternative, either the layer or the gaseous etching atmosphere should be heated.

摘要翻译： 为了研究在晶片上主要由二氧化硅形成的层的蚀刻速率差，将热氧化膜（113）和BSG（117），BPSG（125）和PSG（129）的层叠在晶片上 并且在基本上由氟化氢或氟化氢和水蒸气的混合物组成的气体蚀刻气氛中进行蚀刻。 以比热氧化膜高的蚀刻速率蚀刻各层。 蚀刻速度差是各层的蚀刻速率与热氧化膜的蚀刻速度之差。 这些层可以包括诸如硼和磷的杂质，共同地作为每层的层材料的一部分。 蚀刻速率差取决于层材料。 优选地，气体蚀刻气氛应当具有减压。 或者，水蒸气分压不应大于2000Pa。作为另外的选择，应该加热层或气体蚀刻气氛。