公开(公告)号：US20090197073A1

公开(公告)日：2009-08-06

申请号：US12438836

申请日：2007-08-29

申请人： Hiroko Nakayama ,  Kazuhiro Urashima

发明人： Hiroko Nakayama ,  Kazuhiro Urashima

IPC分类号： C04B35/565 ,  B32B5/16

CPC分类号： B23B27/148 ,  B23B2222/14 ,  B23B2224/04 ,  B23B2226/18 ,  B23B2226/72 ,  C04B35/117 ,  C04B2235/3224 ,  C04B2235/3225 ,  C04B2235/383 ,  C04B2235/3869 ,  C04B2235/3873 ,  C04B2235/5296 ,  C04B2235/5436 ,  C04B2235/5445 ,  C04B2235/764 ,  C04B2235/80 ,  C04B2235/85 ,  C04B2235/96 ,  Y10T428/252

摘要： A cutting insert 1 is made of an aluminum oxide-based composite sintered body constituted by a ternary ceramic material including aluminum oxide, silicon carbide, and a sialon. The sialon in the aluminum oxide-based composite sintered body is Si—Al—O—N as defined by JCPDS No. 32-0026 in X-ray diffraction analysis.

摘要翻译： 切削刀片1由包含氧化铝，碳化硅和塞隆的三元陶瓷材料构成的氧化铝系复合烧结体构成。 氧化铝系复合烧结体中的硅铝氧氮化物是由X射线衍射分析中的JCPDS No.32-0026所定义的Si-Al-O-N。

公开(公告)号：US07951737B2

公开(公告)日：2011-05-31

申请号：US12438836

申请日：2007-08-29

申请人： Hiroko Nakayama ,  Kazuhiro Urashima

发明人： Hiroko Nakayama ,  Kazuhiro Urashima

IPC分类号： C04B35/569 ,  C04B35/599 ,  C04B35/117

CPC分类号： B23B27/148 ,  B23B2222/14 ,  B23B2224/04 ,  B23B2226/18 ,  B23B2226/72 ,  C04B35/117 ,  C04B2235/3224 ,  C04B2235/3225 ,  C04B2235/383 ,  C04B2235/3869 ,  C04B2235/3873 ,  C04B2235/5296 ,  C04B2235/5436 ,  C04B2235/5445 ,  C04B2235/764 ,  C04B2235/80 ,  C04B2235/85 ,  C04B2235/96 ,  Y10T428/252

摘要： A cutting insert 1 is made of an aluminum oxide-based composite sintered body constituted by a ternary ceramic material including aluminum oxide, silicon carbide, and a sialon. The sialon in the aluminum oxide-based composite sintered body is Si—Al—O—N as defined by JCPDS No. 32-0026 in X-ray diffraction analysis.

摘要翻译： 切削刀片1由包含氧化铝，碳化硅和塞隆的三元陶瓷材料构成的氧化铝系复合烧结体构成。 氧化铝系复合烧结体中的硅铝氧氮化物是由X射线衍射分析中的JCPDS No.32-0026所定义的Si-Al-O-N。

公开(公告)号：US07696442B2

公开(公告)日：2010-04-13

申请号：US11445288

申请日：2006-06-02

申请人： Masaki Muramatsu ,  Shinji Yuri ,  Makoto Origuchi ,  Kazuhiro Urashima

发明人： Masaki Muramatsu ,  Shinji Yuri ,  Makoto Origuchi ,  Kazuhiro Urashima

IPC分类号： H05K1/16

CPC分类号： H01L21/6835 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01055 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/351 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/142 ,  H05K1/162 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/096 ,  H05K2201/10674 ,  H05K2201/10712 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/0401

摘要： A wiring board comprising: a core board including a core body and a ceramic sub-core which is accommodated in a sub-core accommodation space that is a through-hole that communicates with major surfaces of the core body or a recess having an opening in a first major surface of the core body; and wiring laminates each formed by resin insulating layers and conductor layers laminated on each of major surfaces of the core board, wherein: a groove-filling portion which fills a gap between the core body and the ceramic sub-core is integral with a lowest resin insulating layer of the first-major-surface-side wiring laminate; and via conductors that are connected to respective conductor patterns formed on a first major surface of the ceramic sub-core penetrate through the lowest resin insulating layer.

摘要翻译： 一种布线板，包括：芯板，其包括芯体和陶瓷子芯，所述芯体容纳在与所述芯体的主表面连通的通孔的子芯容纳空间中，或者具有开口的凹部 核心体的第一个主要表面; 以及由层叠在芯板的各主表面上的树脂绝缘层和导体层形成的布线层叠体，其中，填充芯体与陶瓷副芯之间的间隙的沟槽填充部与最低树脂 第一主表面侧布线层叠体的绝缘层; 并且连接到形成在陶瓷子芯的第一主表面上的相应导体图案的通孔导体穿透最低树脂绝缘层。

公开(公告)号：US20070045815A1

公开(公告)日：2007-03-01

申请号：US11513249

申请日：2006-08-31

申请人： Kazuhiro Urashima ,  Shinji Yuri ,  Manabu Sato ,  Jun Otsuka

发明人： Kazuhiro Urashima ,  Shinji Yuri ,  Manabu Sato ,  Jun Otsuka

IPC分类号： H01L23/04

CPC分类号： H05K1/185 ,  H01G2/06 ,  H01G4/38 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/642 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  H05K1/0231 ,  H05K3/4602 ,  H05K2201/10522 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2924/00 ,  H01L2224/05599

摘要： A wiring board includes a substrate core, ceramic capacitors and a built-up layer. The substrate core has a housing opening portion therein which opens at a core main surface. The ceramic capacitors are accommodated in the housing opening portion and oriented such that the core main surface and a capacitor main surface of each capacitor face the same way. The built-up layer includes semiconductor integrated circuit element mounting areas at various locations on a surface thereof. In the substrate core, each ceramic capacitor is respectively disposed in an area corresponding to each semiconductor integrated circuit element mounting area.

摘要翻译： 布线板包括基板芯，陶瓷电容器和积层。 基板芯具有在芯主表面上开口的壳体开口部分。 陶瓷电容器容纳在壳体开口部分中并且取向为使得每个电容器的芯主表面和电容器主表面相同。 积层在其表面上的各个位置包括半导体集成电路元件安装区域。 在基板芯中，每个陶瓷电容器分别设置在对应于每个半导体集成电路元件安装区域的区域中。

公开(公告)号：US20060272853A1

公开(公告)日：2006-12-07

申请号：US11445288

申请日：2006-06-02

申请人： Masaki Muramatsu ,  Shinji Yuri ,  Makoto Origuchi ,  Kazuhiro Urashima

发明人： Masaki Muramatsu ,  Shinji Yuri ,  Makoto Origuchi ,  Kazuhiro Urashima

IPC分类号： H05K1/11 ,  H05K3/36

CPC分类号： H01L21/6835 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01055 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/351 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/142 ,  H05K1/162 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/096 ,  H05K2201/10674 ,  H05K2201/10712 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/0401

摘要： A wiring board comprising: a core board including a core body and a ceramic sub-core which is accommodated in a sub-core accommodation space that is a through-hole that communicates with major surfaces of the core body or a recess having an opening in a first major surface of the core body; and wiring laminates each formed by resin insulating layers and conductor layers laminated on each of major surfaces of the core board, wherein: a groove-filling portion which fills a gap between the core body and the ceramic sub-core is integral with a lowest resin insulating layer of the first-major-surface-side wiring laminate; and via conductors that are connected to respective conductor patterns formed on a first major surface of the ceramic sub-core penetrate through the lowest resin insulating layer.

摘要翻译： 一种布线板，包括：芯板，其包括芯体和陶瓷子芯，所述芯体容纳在与所述芯体的主表面连通的通孔的子芯容纳空间中，或者具有开口的凹部 核心体的第一个主要表面; 以及由层叠在芯板的各主表面上的树脂绝缘层和导体层形成的布线层叠体，其中，填充芯体与陶瓷副芯之间的间隙的沟槽填充部与最低树脂 第一主表面侧布线层叠体的绝缘层; 并且连接到形成在陶瓷子芯的第一主表面上的相应导体图案的通孔导体穿透最低树脂绝缘层。

公开(公告)号：US07037870B2

公开(公告)日：2006-05-02

申请号：US10353989

申请日：2003-01-30

申请人： Hiroshi Yamamoto ,  Eiji Miura ,  Takeshi Mitsuoka ,  Kazuhiro Urashima

发明人： Hiroshi Yamamoto ,  Eiji Miura ,  Takeshi Mitsuoka ,  Kazuhiro Urashima

IPC分类号： C04B35/195

CPC分类号： H01L21/6838 ,  C04B35/195 ,  C04B2235/3206 ,  C04B2235/3217 ,  C04B2235/3222 ,  C04B2235/3418 ,  C04B2235/3463 ,  C04B2235/3481 ,  C04B2235/36 ,  C04B2235/5436 ,  C04B2235/77 ,  C04B2235/786 ,  C04B2235/80 ,  C04B2235/9607 ,  H01L21/6831 ,  Y10T279/11 ,  Y10T279/23

摘要： A ceramic sintered body comprising from 90 to 99.8% by volume of cordierite and from 0.2 to 10% by volume of mullite based on 100% by weight of a total sum of the contents of the cordierite and the mullite, and having a density of 2.48 g/cm3 or more.

摘要翻译： 一种陶瓷烧结体，其以堇青石和富铝红柱石的总量的100重量％为基准，含有90〜99.8体积％的堇青石和0.2〜10体积％的莫来石，并且密度为2.48 g / cm 3以上。

公开(公告)号：US07973245B2

公开(公告)日：2011-07-05

申请号：US12026838

申请日：2008-02-06

申请人： Masaki Muramatsu ,  Shinji Yuri ,  Kazuhiro Urashima ,  Hiroshi Yamamoto ,  Toshitake Seki ,  Motohiko Sato

发明人： Masaki Muramatsu ,  Shinji Yuri ,  Kazuhiro Urashima ,  Hiroshi Yamamoto ,  Toshitake Seki ,  Motohiko Sato

IPC分类号： H05K1/16

CPC分类号： H01G2/06 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/10 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/0102 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： An intermediate board has a board core formed by a main core body and a sub-core portion. The main core body has a plate-like shape and includes an open sub-core housing portion in which the sub-core portion is housed. A first terminal array of the board core has an area that overlaps an orthogonal projection of the sub-core portion. The latter incorporates a laminated ceramic capacitor formed by first and second conductor layers with a ceramic (dielectric) layer therebetween. The first layer is connected to first and second side terminals of a first type while the second layer is connected to first and second side terminals of a second type. The housing portion has an inner edge which, in cross section, is of a quadrate shape, and a radius portion is formed at each corner having a dimension of between 0.1 and 2 mm.

摘要翻译： 中间板具有由主芯体和副芯部形成的板芯。 主芯体具有板状形状，并且包括其中容纳有副芯部的开放子芯容纳部。 板芯的第一端子阵列具有与子芯部的正交突起重叠的区域。 后者包括由其间具有陶瓷（电介质）层的第一和第二导体层形成的层叠陶瓷电容器。 第一层连接到第一类型的第一和第二侧端子，而第二层连接到第二类型的第一和第二侧端子。 壳体部分具有横截面为正方形的内边缘，并且在每个角部处形成具有0.1至2mm的尺寸的半径部分。

公开(公告)号：US20080223607A1

公开(公告)日：2008-09-18

申请号：US12026838

申请日：2008-02-06

申请人： Masaki MURAMATSU ,  Shinji Yuri ,  Kazuhiro Urashima ,  Hiroshi Yamamoto ,  Toshitake Seki ,  Motohiko Sato

发明人： Masaki MURAMATSU ,  Shinji Yuri ,  Kazuhiro Urashima ,  Hiroshi Yamamoto ,  Toshitake Seki ,  Motohiko Sato

IPC分类号： H05K1/16

CPC分类号： H01G2/06 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/10 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/0102 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： An intermediate board has a board core formed by a main core body and a sub-core portion. The main core body has a plate-like shape and includes an open sub-core housing portion in which the sub-core portion is housed. A first terminal array of the board core has an area that overlaps an orthogonal projection of the sub-core portion. The latter incorporates a laminated ceramic capacitor formed by first and second conductor layers with a ceramic (dielectric) layer therebetween. The first layer is connected to first and second side terminals of a first type while the second layer is connected to first and second side terminals of a second type. The housing portion has an inner edge which, in cross section, is of a quadrate shape, and a radius portion is formed at each corner having a dimension of between 0.1 and 2 mm.

摘要翻译： 中间板具有由主芯体和副芯部形成的板芯。 主芯体具有板状形状，并且包括其中容纳有副芯部的开放子芯容纳部。 板芯的第一端子阵列具有与子芯部的正交突起重叠的区域。 后者包括由其间具有陶瓷（电介质）层的第一和第二导体层形成的层叠陶瓷电容器。 第一层连接到第一类型的第一和第二侧端子，而第二层连接到第二类型的第一和第二侧端子。 壳体部分具有横截面为正方形的内边缘，并且在每个角部处形成具有0.1至2mm的尺寸的半径部分。

公开(公告)号：US07317165B2

公开(公告)日：2008-01-08

申请号：US10874531

申请日：2004-06-24

申请人： Hajime Saiki ,  Kazuhiro Urashima

发明人： Hajime Saiki ,  Kazuhiro Urashima

IPC分类号： H05K1/16

CPC分类号： H05K3/305 ,  H01L21/563 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K7/1061 ,  H05K2201/10734 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/05599

摘要： An intermediate substrate comprising: an intermediate substrate body containing an insulating material, and having a first face to be mounted with an semiconductor element and a second face opposing to said first face; and a semiconductor element mounting area including a plurality of first face terminals arranged on said first face, and being surrounded by an outermost periphery of said plurality of first face terminals, wherein a center of said semiconductor element mounting area is eccentric with respect to a center of said first face.

摘要翻译： 1.一种中间基板，包括：中间基板主体，其包含绝缘材料，并且具有要安装有半导体元件的第一面和与所述第一面相对的第二面; 以及半导体元件安装区域，包括布置在所述第一面上的多个第一面接线端子，并且被所述多个第一面接线端子的最外周围包围，其中所述半导体元件安装区域的中心相对于中心偏心 的第一面。

公开(公告)号：US20070064375A1

公开(公告)日：2007-03-22

申请号：US11513039

申请日：2006-08-31

申请人： Kazuhiro Urashima ,  Shinji Yuri ,  Manabu Sato ,  Yasuhiro Sugimoto

发明人： Kazuhiro Urashima ,  Shinji Yuri ,  Manabu Sato ,  Yasuhiro Sugimoto

IPC分类号： H01G4/06

CPC分类号： H05K1/185 ,  H01G2/06 ,  H01G4/385 ,  H01L23/49816 ,  H01L23/50 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/3025 ,  H05K1/0231 ,  H05K3/4602 ,  H05K2201/10045 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2224/05599

摘要： A circuit board (10, 10″, 10″′) comprising: a board core (11) having a main core surface (12) and a rear core surface (13); a ceramic capacitor (101, 101′, 101″, 101″′, 101″″, 101″″′, 101″″″) having a main capacitor surface (102) and a rear capacitor surface (103), having a structure in which a first inner electrode layer (141) and a second inner electrode layer (142) are alternately stacked with a ceramic dielectric layer (105) interposed therebetween, and having a plurality of capacitor function units (107, 108) being electrically independent from each other, the ceramic capacitor (101, 101′, 101″, 101″′, 101″″, 101″″′, 101″″″) being buried in the board core (11) in a state where the main core surface (12) and the main capacitor surface (102) are directed in a same direction; and a buildup layer (31) having a structure in which an interlayer insulating layer (33, 35) and a conductor layer (42) are alternately stacked on the main core surface (12) and the main capacitor surface (102) and having a semiconductor integrated circuit device mounting region (23, 51, 52) for mounting a semiconductor integrated circuit device (21, 53, 54) having a plurality of processor cores (24, 25) on a surface (39) of the buildup layer (31), wherein the plurality of capacitor function units (107, 108) are capable of being electrically connected to the plurality of processor cores (24, 25), respectively.

摘要翻译： 一种电路板（10,10“，10”），包括：具有主芯表面（12）和后芯表面（13）的板芯（11）; 具有主电容器表面（102）和后部电容器（102）的陶瓷电容器（101,101'，101“，101”'，101“'，101”'，101“'，101”'，101“ 电容器表面（103），其具有第一内部电极层（141）和第二内部电极层（142）与陶瓷介电层（105）交替层叠的结构，并且具有多个电容器功能单元 （101,101'，101“，101”，101“，101”，101“，101”，101“，101”，101“ ）以主芯表面（12）和主电容器表面（102）指向相同方向的状态埋在板芯（11）中; 以及具有层间绝缘层（33,35）和导体层（42）在主芯面（12）和主电容器表面（102）上交替层叠的结构的积层（31），具有 半导体集成电路器件安装区域（23,51,52），用于安装具有多个处理器核心（24,25）的半导体集成电路器件（21,53,54），所述多个处理器核心（24,25）在所述生成层（31）的表面（39）上 ），其中所述多个电容器功能单元（107,108）能够分别电连接到所述多个处理器核（24,25）。