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公开(公告)号：US20060016779A1
公开(公告)日：2006-01-26
申请号：US11146235
申请日：2005-06-07
IPC分类号： H01B13/00
CPC分类号： H05K3/243 , H05K3/0052 , H05K3/108 , H05K3/426 , H05K3/427 , H05K2203/0361 , H05K2203/0542
摘要： A method of manufacturing a wiring board by utilizing electro plating characterized in that: when a wiring pattern is formed on the board by utilizing electro plating, an unnecessary portion does not remain on the wiring pattern. The method comprises: first electroless plating layers (19) are formed on both sides of an insulating substrate (1), which are covered with metallic foils (17) in advance, on which first electro plating layers (21) are formed; wiring patterns are formed by etching so as not to extend to the end edge of the substrate; second electroless plating layers (41) are formed on all of the surfaces of the substrate; a plating resist pattern (43) is formed so that only a predetermined portion of the wiring patterns is exposed; a second electro plating layer (27, 29) is formed on the predetermined portion of the wiring patterns by supplying an electric power from the second electroless plating layers; the plating resist pattern and the second electroless plating layers are removed; and a solder resist (45) is formed so that predetermined portions of the wiring patterns are exposed.
摘要翻译： 一种利用电镀制造布线板的方法，其特征在于：当利用电镀在基板上形成布线图形时，不需要的部分不残留在布线图案上。 该方法包括：首先在绝缘基板（1）的两侧形成第一化学镀层（19），绝缘基板（1）预先被金属箔（17）覆盖，其上形成有第一电镀层（21） 通过蚀刻形成布线图案，以便不延伸到基板的端边缘; 在基板的所有表面上形成第二无电镀层（41） 形成电镀抗蚀剂图案（43），使得只有布线图案的预定部分露出; 通过从第二化学镀层供给电力，在布线图案的预定部分上形成第二电镀层（27,29）; 去除电镀抗蚀剂图案和第二无电镀层; 并且形成阻焊剂（45），使得布线图案的预定部分露出。
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公开(公告)号：US07347949B2
公开(公告)日：2008-03-25
申请号：US11146235
申请日：2005-06-07
IPC分类号： H01B13/00
CPC分类号： H05K3/243 , H05K3/0052 , H05K3/108 , H05K3/426 , H05K3/427 , H05K2203/0361 , H05K2203/0542
摘要： A method of manufacturing a wiring board by utilizing electro plating characterized in that: when a wiring pattern is formed on the board by utilizing electro plating, an unnecessary portion does not remain on the wiring pattern. The method comprises: first electroless plating layers (19) are formed on both sides of an insulating substrate (1), which are covered with metallic foils (17) in advance, on which first electro plating layers (21) are formed; wiring patterns are formed by etching so as not to extend to the end edge of the substrate; second electroless plating layers (41) are formed on all of the surfaces of the substrate; a plating resist pattern (43) is formed so that only a predetermined portion of the wiring patterns is exposed; a second electro plating layer (27, 29) is formed on the predetermined portion of the wiring patterns by supplying an electric power from the second electroless plating layers; the plating resist pattern and the second electroless plating layers are removed; and a solder resist (45) is formed so that predetermined portions of the wiring patterns are exposed.
摘要翻译： 一种利用电镀制造布线板的方法，其特征在于：当利用电镀在基板上形成布线图形时，不需要的部分不残留在布线图案上。 该方法包括：首先在绝缘基板（1）的两侧形成第一化学镀层（19），绝缘基板（1）预先被金属箔（17）覆盖，其上形成有第一电镀层（21） 通过蚀刻形成布线图案，以便不延伸到基板的端边缘; 在基板的所有表面上形成第二无电镀层（41） 形成电镀抗蚀剂图案（43），使得只有布线图案的预定部分露出; 通过从第二化学镀层供给电力，在布线图案的预定部分上形成第二电镀层（27,29）; 去除电镀抗蚀剂图案和第二无电镀层; 并且形成阻焊剂（45），使得布线图案的预定部分露出。
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公开(公告)号：US08043514B2
公开(公告)日：2011-10-25
申请号：US12003673
申请日：2007-12-28
IPC分类号： H01B13/00
CPC分类号： H05K3/243 , H05K3/0052 , H05K3/108 , H05K3/426 , H05K3/427 , H05K2203/0361 , H05K2203/0542
摘要： When a wiring pattern is formed on a wiring board utilizing electroplating, an unnecessary portion is removed by proceeding as follows. First electroless plating layers are formed on both sides of an insulating substrate, which are covered with metallic foils in advance. On the first electroplating layers, wiring patterns are formed by etching so as not to extend to the end edge of the substrate. Then, a plating resist pattern is formed so that only a predetermined portion of the wiring patterns is exposed and a second electroplating layer is formed on the predetermined portion of the wiring patterns by supplying electric power from second electroless plating layers. Finally, the plating resist pattern and the second electroless plating layers are removed, and a solder resist is formed so that predetermined portions of the wiring patterns are exposed.
摘要翻译： 当利用电镀在布线板上形成布线图形时，如下进行移除不需要的部分。 首先在绝缘基板的两面上形成有预先用金属箔覆盖的化学镀层。 在第一电镀层上，通过蚀刻形成布线图案，以便不延伸到基板的端部边缘。 然后，通过从第二化学镀层提供电力，形成电镀抗蚀剂图案，使得只有布线图案的预定部分露出，并且在布线图案的预定部分上形成第二电镀层。 最后，去除电镀抗蚀剂图案和第二无电解镀层，形成阻焊剂，使布线图案的预定部分露出。
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公开(公告)号：US20080116079A1
公开(公告)日：2008-05-22
申请号：US12003673
申请日：2007-12-28
CPC分类号： H05K3/243 , H05K3/0052 , H05K3/108 , H05K3/426 , H05K3/427 , H05K2203/0361 , H05K2203/0542
摘要： When a wiring pattern is formed on a wiring board utilizing electroplating, an unnecessary portion is removed by proceeding as follows. First electroless plating layers are formed on both sides of an insulating substrate, which are covered with metallic foils in advance. On the first electroplating layers, wiring patterns are formed by etching so as not to extend to the end edge of the substrate. Then, a plating resist pattern is formed so that only a predetermined portion of the wiring patterns is exposed and a second electroplating layer is formed on the predetermined portion of the wiring patterns by supplying electric power from second electroless plating layers. Finally, the plating resist pattern and the second electroless plating layers are removed, and a solder resist is formed so that predetermined portions of the wiring patterns are exposed.
摘要翻译： 当利用电镀在布线板上形成布线图形时，如下进行移除不需要的部分。 首先在绝缘基板的两面上形成有预先用金属箔覆盖的化学镀层。 在第一电镀层上，通过蚀刻形成布线图案，以便不延伸到基板的端部边缘。 然后，通过从第二化学镀层提供电力，形成电镀抗蚀剂图案，使得只有布线图案的预定部分露出，并且在布线图案的预定部分上形成第二电镀层。 最后，去除电镀抗蚀剂图案和第二无电解镀层，形成阻焊剂，使布线图案的预定部分露出。
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5.发明授权Semiconductor device package, method of manufacturing the same, and semiconductor device 有权半导体器件封装，其制造方法和半导体器件公开(公告)号：US07453141B2
公开(公告)日：2008-11-18
申请号：US11354361
申请日：2006-02-15
CPC分类号： H01L23/49827 , H01L23/13 , H01L23/49822 , H01L23/50 , H01L24/48 , H01L24/49 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/4824 , H01L2224/49 , H01L2224/73215 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01019 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/15311 , H01L2924/181 , H01L2924/3011 , H05K3/403 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A semiconductor device package is provided which can achieve speeding-up thereof. The semiconductor device package includes: a board which has at least one of a ground plane and a power plane; at least one connecting conductor portion which is formed on an inner wall surface of an opening portion of the board and electrically connected to the corresponding plane; at least one bonding pattern which is formed on a front surface layer portion of the board in the vicinity of an edge of the opening portion, and connected to the corresponding connecting conductor portion; and a second external connection portion which is formed on the side of the front surface layer of the board, and electrically connected to the corresponding plane, respectively, through a through-hole conductor portion formed in the board.
摘要翻译： 提供一种可实现其加速的半导体器件封装。 半导体器件封装包括：具有地平面和电源平面中的至少一个的板; 至少一个连接导体部分，其形成在所述电路板的开口部分的内壁表面上并电连接到相应的平面; 至少一个接合图形，形成在所述基板的前表面层部分的所述开口部分的边缘附近，并连接到相应的连接导体部分; 以及第二外部连接部，其形成在所述基板的前表面侧的侧面，并分别通过形成在所述基板上的贯通孔导体部与所述平面电连接。
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6.发明申请Semiconductor device package, method of manufacturing the same, and semiconductor device 有权半导体器件封装，其制造方法和半导体器件公开(公告)号：US20060189178A1
公开(公告)日：2006-08-24
申请号：US11354361
申请日：2006-02-15
IPC分类号： H01R12/00
CPC分类号： H01L23/49827 , H01L23/13 , H01L23/49822 , H01L23/50 , H01L24/48 , H01L24/49 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/4824 , H01L2224/49 , H01L2224/73215 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01019 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/15311 , H01L2924/181 , H01L2924/3011 , H05K3/403 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A semiconductor device package is provided which can achieve speeding-up thereof. The semiconductor device package includes: a board which has at least one of a ground plane and a power plane; at least one connecting conductor portion which is formed on an inner wall surface of an opening portion of the board and electrically connected to the corresponding plane; at least one bonding pattern which is formed on a front surface layer portion of the board in the vicinity of an edge of the opening portion, and connected to the corresponding connecting conductor portion; and a second external connection portion which is formed on the side of the front surface layer of the board, and electrically connected to the corresponding plane, respectively, through a through-hole conductor portion formed in the board.
摘要翻译： 提供一种可实现其加速的半导体器件封装。 半导体器件封装包括：具有地平面和电源平面中的至少一个的板; 至少一个连接导体部分，其形成在所述电路板的开口部分的内壁表面上并电连接到相应的平面; 至少一个接合图形，形成在所述基板的前表面层部分的所述开口部分的边缘附近，并连接到相应的连接导体部分; 以及第二外部连接部，其形成在所述基板的前表面侧的侧面，并分别通过形成在所述基板上的贯通孔导体部与所述平面电连接。
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7.发明授权Pipeline computer dividing a variable-length data-handling instruction into fixed-length data-handling instructions 失效管线计算机将可变长度数据处理指令分为固定长度的数据处理指令公开(公告)号：US06502187B1
公开(公告)日：2002-12-31
申请号：US09440134
申请日：1999-11-15
申请人： Hiroshi Miyagawa
发明人： Hiroshi Miyagawa
IPC分类号： G06F9312
CPC分类号： G06F9/30043 , G06F9/3016 , G06F9/3017 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： The present invention provides a pipelined computer which processes variable-length data without using branch instructions for speedy execution of a variable-length data-handling software instruction. Upon receiving a variable-length data-handling instruction from an instruction supply unit 1, an instruction division unit 2 divides the instruction into a plurality of derived micro instructions that handle fixed-length data. A reservation station 5 sends the derived micro instructions to an execution unit 6 and a redundant instruction detection unit 9 in a sequence in which the derived micro instructions were generated during the division. The redundant instruction detection unit 9 monitors the remaining derived micro instructions. An instruction deletion control unit 8 deletes redundant micro instructions in the reservation station 5. An instruction end operation unit 7 sets the state of the redundant derived micro instructions in the reorder buffer 4 to “execution completed state”.
摘要翻译： 本发明提供了一种流水线计算机，其处理可变长度数据而不使用用于快速执行可变长度数据处理软件指令的分支指令。 指令分割单元2从指令提供单元1接收到可变长度的数据处理指令时，将该指令划分为处理固定长度数据的多个导出的微指令。 保留站5以分割之后产生导出的微指令的顺序将派生的微指令发送到执行单元6和冗余指令检测单元9。 冗余指令检测单元9监视剩余的导出的微指令。 指令删除控制单元8删除保留站5中的冗余微指令。指令结束操作单元7将重排序缓冲器4中的冗余导出微指令的状态设置为“执行完成状态”。
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公开(公告)号：US10001091B2
公开(公告)日：2018-06-19
申请号：US15345715
申请日：2016-11-08
申请人： Brian M. Weiss , Walter Weissman , Tilman W. Beutel , John F. Brody , Eugine Choi , Wenjun Li , Paul D. Madiara , Chris E. Esther Kliewer , Karl G. Strohmaier , Scott J. Weigel , Brett Loveless , Makoto Kioke , Hiroshi Miyagawa
发明人： Brian M. Weiss , Walter Weissman , Tilman W. Beutel , John F. Brody , Eugine Choi , Wenjun Li , Paul D. Madiara , Chris E. Esther Kliewer , Karl G. Strohmaier , Scott J. Weigel , Brett Loveless , Makoto Kioke , Hiroshi Miyagawa
IPC分类号： F01N3/20 , F02M27/02 , C10L3/10 , F02B43/12 , F02B51/02 , F02M21/02 , B01J29/44 , B01J29/74 , B01J29/80 , C10L3/00 , C01B3/40 , B01J23/63 , B01J29/068 , F02M26/35 , F02M26/36 , F02M26/20 , B01J21/04 , B01J21/08 , B01J23/10 , B01J23/46 , B01J29/00 , B01J29/70 , B01J29/85 , C10L3/08 , F02B37/013 , F02B43/10 , F02M26/05
CPC分类号： F02M27/02 , B01J21/04 , B01J21/08 , B01J23/10 , B01J23/464 , B01J23/63 , B01J29/005 , B01J29/068 , B01J29/44 , B01J29/70 , B01J29/743 , B01J29/80 , B01J29/85 , B01J2523/00 , C01B3/40 , C01B2203/0233 , C01B2203/0238 , C01B2203/1047 , C01B2203/1064 , C01B2203/107 , C01B2203/1082 , C01B2203/1241 , C01B2203/1247 , C01B2203/84 , C10L3/00 , C10L3/08 , C10L3/10 , C10L2230/22 , C10L2270/02 , C10L2290/02 , C10L2290/06 , C10L2290/24 , F01N3/20 , F02B37/013 , F02B43/12 , F02B51/02 , F02B61/02 , F02B2043/103 , F02M21/0227 , F02M26/05 , F02M26/20 , F02M26/35 , F02M26/36 , Y02P20/142 , Y02P20/52 , Y02T10/126 , Y02T10/32 , B01J2523/31 , B01J2523/3706 , B01J2523/3712 , B01J2523/48 , B01J2523/822
摘要： Catalyst compositions suitable for use in the exhaust gas recycle stream of an internal combustion engine are provided. Such catalyst compositions typically provide significant amounts of methane in addition to syngas. A reformer incorporating such a catalyst for use in an exhaust gas recycle portion of an internal combustion engine powertrain is described. A powertrain incorporating such a reformer, a method of increasing the octane rating of an exhaust gas recycle stream, and a method of operating an internal combustion engine using methane-assisted combustion are also described.
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公开(公告)号：US09617490B2
公开(公告)日：2017-04-11
申请号：US14566877
申请日：2014-12-11
申请人： Brian Michael Weiss , Walter Weissman , Tilman Wolfram Beutel , John Francis Brody , Eugine Choi , Wenjun Li , Paul Dmitri Madiara , Chris Esther Kliewer , Karl Gottlieb Strohmaier , Scott J. Weigel , Brett Loveless , Makota Koike , Hiroshi Miyagawa
发明人： Brian Michael Weiss , Walter Weissman , Tilman Wolfram Beutel , John Francis Brody , Eugine Choi , Wenjun Li , Paul Dmitri Madiara , Chris Esther Kliewer , Karl Gottlieb Strohmaier , Scott J. Weigel , Brett Loveless , Makota Koike , Hiroshi Miyagawa
IPC分类号： B01J29/44 , C10L3/10 , F01N3/20 , F02B43/12 , F02B61/02 , F02M21/02 , F02M27/02 , B01J29/74 , B01J29/80 , C10L3/00 , C01B3/40 , B01J23/63 , B01J29/068 , F02M26/35 , F02M26/36 , F02B37/013 , F02B43/10 , F02M26/05
CPC分类号： F02M27/02 , B01J21/04 , B01J21/08 , B01J23/10 , B01J23/464 , B01J23/63 , B01J29/005 , B01J29/068 , B01J29/44 , B01J29/70 , B01J29/743 , B01J29/80 , B01J29/85 , B01J2523/00 , C01B3/40 , C01B2203/0233 , C01B2203/0238 , C01B2203/1047 , C01B2203/1064 , C01B2203/107 , C01B2203/1082 , C01B2203/1241 , C01B2203/1247 , C01B2203/84 , C10L3/00 , C10L3/08 , C10L3/10 , C10L2230/22 , C10L2270/02 , C10L2290/02 , C10L2290/06 , C10L2290/24 , F01N3/20 , F02B37/013 , F02B43/12 , F02B51/02 , F02B61/02 , F02B2043/103 , F02M21/0227 , F02M26/05 , F02M26/20 , F02M26/35 , F02M26/36 , Y02P20/142 , Y02P20/52 , Y02T10/126 , Y02T10/32 , B01J2523/31 , B01J2523/3706 , B01J2523/3712 , B01J2523/48 , B01J2523/822
摘要： Catalyst compositions suitable for use in the exhaust gas recycle stream of an internal combustion engine are provided. Such catalyst compositions typically provide significant amounts of methane in addition to syngas. A reformer incorporating such a catalyst for use in an exhaust gas recycle portion of an internal combustion engine powertrain is described. A powertrain incorporating such a reformer, a method of increasing the octane rating of an exhaust gas recycle stream, and a method of operating an internal combustion engine using methane-assisted combustion are also described.
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公开(公告)号：US20110074171A1
公开(公告)日：2011-03-31
申请号：US12892748
申请日：2010-09-28
申请人： Keisuke Maehara , Hiroshi Miyagawa
发明人： Keisuke Maehara , Hiroshi Miyagawa
CPC分类号： B25J9/1612 , B25J9/1679 , G05B2219/39487 , G05B2219/39543
摘要： An object grasping control method, in which an object grasping control apparatus grasps a plurality of graspable members using a grasping unit, includes recognizing at least one of a shape, position, and attitude of each of the plurality of graspable members, setting, based on at least of one of the shape, position, and attitude of each of the plurality of graspable members, an attitude range as a graspable attitude range in which each of the plurality of graspable members and the grasping unit do not interfere with each other for each of the plurality of graspable members, and setting, as a grasping target to be grasped by the grasping unit, a graspable member, among the plurality of graspable members, the set graspable attitude range of which is greater than a predetermined threshold value.
摘要翻译： 一种物体抓持控制方法，其中物体抓持控制装置使用抓握单元抓握多个可抓握构件，包括识别多个可抓握构件中的每一个的形状，位置和姿态中的至少一个，基于 至少所述多个所述可抓握构件的形状，位置和姿态中的至少一个，作为所述多个所述可抓握构件和所述把持单元中的每一个彼此不干扰的可握持姿态范围的姿态范围， 并且将所述可抓握姿势范围大于预定阈值的所述可抓握构件中的可握持构件设置为由所述把持单元抓握的把持对象。
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