公开(公告)号：US20100124817A1

公开(公告)日：2010-05-20

申请号：US12694715

申请日：2010-01-27

申请人： Ho-Young KIM ,  Chang-Ki HONG ,  Bo-Un YOON ,  Joon-Sang PARK

发明人： Ho-Young KIM ,  Chang-Ki HONG ,  Bo-Un YOON ,  Joon-Sang PARK

IPC分类号： H01L21/3213 ,  H01L21/28

CPC分类号： H01L21/76897 ,  H01L21/7684 ,  H01L27/10873 ,  H01L27/10885

摘要： A method of fabricating a self-aligned contact pad (SAC) includes forming stacks of a conductive line and a capping layer on a semiconductor substrate, spacers covering sidewalls of the stacks, and an insulation layer filling gaps between the stacks and exposing the top of the capping layer, etching the capping layer to form damascene grooves, forming a plurality of first etching masks with a material different from that of the capping layer to fill the damascene grooves without covering the top of the insulation layer, and forming a second etching mask having an opening region that exposes some of the first etching masks and a portion of the insulation layer located between the first etching masks. The method further includes etching the portion of the insulation layer exposed by the opening region using the first and second etching masks to form a plurality of opening holes, removing the second etching mask, forming a conductive layer filling the opening holes to cover the remaining first etching masks and performing a chemical mechanical polishing (CMP) process on the conductive layer using the capping layer as a polishing end point to remove the first etching masks such that a plurality of SAC pads separated from each other are formed that fill the opening holes.

摘要翻译： 一种制造自对准接触焊盘（SAC）的方法包括在半导体衬底上形成导电线和覆盖层的叠层，覆盖堆叠的侧壁的间隔物和填充堆叠之间的间隙的绝缘层， 覆盖层，蚀刻覆盖层以形成镶嵌槽，用不同于覆盖层的材料形成多个第一蚀刻掩模以填充镶嵌槽而不覆盖绝缘层的顶部，以及形成第二蚀刻掩模 具有暴露一些第一蚀刻掩模的开口区域和位于第一蚀刻掩模之间的绝缘层的一部分。 该方法还包括使用第一和第二蚀刻掩模蚀刻由开口区域暴露的绝缘层的部分，以形成多个开孔，去除第二蚀刻掩模，形成填充开孔的导电层以覆盖剩余的第一 蚀刻掩模并使用覆盖层作为抛光终点在导电层上进行化学机械抛光（CMP）工艺，以去除第一蚀刻掩模，从而形成填充开孔的彼此分离的多个SAC焊盘。

公开(公告)号：US20150097251A1

公开(公告)日：2015-04-09

申请号：US14569597

申请日：2014-12-12

申请人： Byoung-Ho KWON ,  Cheol KIM ,  Ho-Young KIM ,  Se-Jung PARK ,  Myeong-Cheol KIM ,  Bo-Kyeong KANG ,  Bo-Un YOON ,  Jae-Kwang CHOI ,  Si-Young CHOI ,  Suk-Hoon JEONG ,  Geum-Jung SEONG ,  Hee-Don JEONG ,  Yong-Joon CHOI ,  Ji-Eun HAN

发明人： Byoung-Ho KWON ,  Cheol KIM ,  Ho-Young KIM ,  Se-Jung PARK ,  Myeong-Cheol KIM ,  Bo-Kyeong KANG ,  Bo-Un YOON ,  Jae-Kwang CHOI ,  Si-Young CHOI ,  Suk-Hoon JEONG ,  Geum-Jung SEONG ,  Hee-Don JEONG ,  Yong-Joon CHOI ,  Ji-Eun HAN

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L29/66

CPC分类号： H01L29/7853 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

摘要： Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

摘要翻译： 半导体器件可以包括具有第一半导体鳍片的半导体衬底，第一半导体鳍片端对端与第二半导体对准，第二半导体在第一和第二半导体鳍片的相对端之间具有凹陷。 第一绝缘体图案形成在第一和第二半导体鳍片的相邻侧壁附近，并且在第一凹部内形成第二绝缘体图案。 第二绝缘体图案可以具有高于第一绝缘体图案的顶表面的顶表面，例如高于鳍片（或更高或更低）的顶表面的高度。 第一和第二栅极沿第一半导体鳍片的侧壁和顶表面延伸。 可以在第二绝缘体的顶表面上形成伪栅电极。 还公开了其制造方法和修改方案。

公开(公告)号：US20120152460A1

公开(公告)日：2012-06-21

申请号：US13238308

申请日：2011-09-21

申请人： Ho-Young KIM ,  Seung-Jae LEE ,  Bo-Un YOON

发明人： Ho-Young KIM ,  Seung-Jae LEE ,  Bo-Un YOON

IPC分类号： C23F1/08

CPC分类号： G03F1/50 ,  G03F1/44 ,  H01L21/28 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66628

摘要： A test mask set includes a first test mask having a plurality of gate pattern areas disposed therein, each of the plurality of gate pattern areas having one or more gate patterns; and a second test mask having a plurality of active pattern areas disposed therein, each of the plurality of active pattern areas having one or more active patterns. The gate patterns formed in different areas among the plurality of gate pattern areas differ in at least one of a gate spacing or a gate width. The active patterns formed in different areas among the plurality of active pattern areas differ in at least one of an active spacing or an active width

摘要翻译： 测试掩模组包括第一测试掩模，其中设置有多个栅极图案区域，多个栅极图案区域中的每一个具有一个或多个栅极图案; 以及设置在其中的多个有源图案区域的第二测试掩模，所述多个有源图案区域中的每一个具有一个或多个活动图案。 形成在多个栅极图案区域中的不同区域中的栅极图案在栅极间隔或栅极宽度中的至少一个方面不同。 形成在多个有源图案区域中的不同区域中的活动图案在有效间隔或有效宽度中的至少一个方面不同

公开(公告)号：US20160268414A1

公开(公告)日：2016-09-15

申请号：US15000495

申请日：2016-01-19

申请人： Sang-Jine PARK ,  Keun-Hee BAI ,  Kyoung-Hwan YEO ,  Bo-Un YOON ,  Kee-Sang KWON ,  Do-Hyoung KIM ,  Ha-Young JEON ,  Seung-Seok HA

发明人： Sang-Jine PARK ,  Keun-Hee BAI ,  Kyoung-Hwan YEO ,  Bo-Un YOON ,  Kee-Sang KWON ,  Do-Hyoung KIM ,  Ha-Young JEON ,  Seung-Seok HA

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/49

CPC分类号： H01L29/785 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0657 ,  H01L29/4238 ,  H01L29/495 ,  H01L29/7848

摘要： Semiconductor devices are provided including a first active fin extending in a first direction and a second active fin spaced apart from the first active fin in a second direction perpendicular to the first direction, the second active fin extending in the first direction, the second active fin having a longer side shorter than a length of a longer side of the first active fin. A first dummy gate extends in the second direction overlapping a first end of each of the first and second active fins. A first metal gate extends in the second direction intersecting the first active fin and overlapping a second end of the second active fin. A first insulating gate extends in the second direction intersecting the first active fin. The first insulating gate extends into the first active fin.

摘要翻译： 提供了半导体器件，其包括在垂直于第一方向的第二方向上沿第一方向延伸的第一有源鳍片和与第一有源鳍片间隔开的第二有源鳍片，第二有源鳍片沿第一方向延伸，第二有源鳍片 具有比第一活性翅片的长边的长度短的长边。 第一伪栅极在第二方向上延伸，与第一和第二活性鳍片中的每一个的第一端重叠。 第一金属栅极在与第一有效鳍交叉的第二方向上延伸并与第二活动鳍片的第二端重叠。 第一绝缘栅极在与第一活性鳍相交的第二方向上延伸。 第一绝缘栅延伸到第一活性鳍。

公开(公告)号：US20150187946A1

公开(公告)日：2015-07-02

申请号：US14455036

申请日：2014-08-08

申请人： Sang-Jine PARK ,  Bo-Un YOON ,  Ha-Young JEON ,  Byung-Kwon CHO ,  Jeong-Nam HAN

发明人： Sang-Jine PARK ,  Bo-Un YOON ,  Ha-Young JEON ,  Byung-Kwon CHO ,  Jeong-Nam HAN

IPC分类号： H01L29/78 ,  H01L29/49 ,  H01L27/088 ,  H01L29/423

CPC分类号： H01L29/66545 ,  H01L21/28114 ,  H01L27/0886 ,  H01L29/42376 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

摘要： A semiconductor device includes a gate spacer defining a trench. The trench includes a first part and a second part sequentially positioned on a substrate. An inner surface of the first part has a slope of an acute angle and an inner surface of the second part has a slope of a right angle or obtuse angle with respect to the substrate. A gate electrode fills at least a portion of the trench.

摘要翻译： 半导体器件包括限定沟槽的栅极间隔。 沟槽包括顺序地位于基板上的第一部分和第二部分。 第一部分的内表面具有锐角的斜面，并且第二部分的内表面具有相对于基底的直角或钝角的斜率。 栅电极填充沟槽的至少一部分。

公开(公告)号：US20160315045A1

公开(公告)日：2016-10-27

申请号：US15016376

申请日：2016-02-05

申请人： Jae-Jik BAEK ,  Kee-Sang KWON ,  Sang-Jine PARK ,  Bo-Un YOON

发明人： Jae-Jik BAEK ,  Kee-Sang KWON ,  Sang-Jine PARK ,  Bo-Un YOON

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/088

CPC分类号： H01L23/528 ,  H01L21/76804 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76865 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/088 ,  H01L27/0886

摘要： The semiconductor device may include an insulating interlayer on the substrate, the substrate including a contact region at an upper portion thereof, a main contact plug penetrating through the insulating interlayer and contacting the contact region, the main contact plug having a pillar shape and including a first barrier pattern and a first metal pattern, and an extension pattern surrounding on an upper sidewall of the main contact plug, the extension pattern including a barrier material. In the semiconductor device, an alignment margin between the contact structure and an upper wiring thereon may increase. Also, a short failure between the contact structure and the gate electrode may be reduced.

摘要翻译： 半导体器件可以在衬底上包括绝缘中间层，衬底包括其上部的接触区域，穿过绝缘中间层并接触接触区域的主接触插塞，具有柱形形状的主接触插塞包括 第一屏障图案和第一金属图案，以及围绕主接触插塞的上侧壁的延伸图案，延伸图案包括阻挡材料。 在半导体器件中，接触结构和其上的布线之间的对准边缘可能增加。 此外，可以减小接触结构和栅电极之间的短路故障。

公开(公告)号：US20130023100A1

公开(公告)日：2013-01-24

申请号：US13479679

申请日：2012-05-24

申请人： Sang-Jine PARK ,  Doo-Sung YUN ,  Bo-Un YOON ,  Jeong-Nam HAN ,  Kee-Sang KWON ,  Won-Sang CHOI

发明人： Sang-Jine PARK ,  Doo-Sung YUN ,  Bo-Un YOON ,  Jeong-Nam HAN ,  Kee-Sang KWON ,  Won-Sang CHOI

IPC分类号： H01L21/336

CPC分类号： H01L21/823425 ,  H01L21/02063 ,  H01L21/28518 ,  H01L21/31116 ,  H01L21/76814 ,  H01L21/76897 ,  H01L21/823475 ,  H01L29/78

摘要： A method of fabricating a semiconductor device, the method including forming on a substrate a transistor that includes a gate electrode and a source and drain region, forming an interlayer insulating film on the transistor, forming a contact hole in the interlayer insulating film to expose a top surface of the source and drain region, and a thin film is formed at an interface between the contact hole and the exposed top surface of the source and drain region. The method further including selectively removing at least a portion of the thin film by performing an etching process in a non-plasma atmosphere, forming an ohmic contact film on the source and drain region where at least a portion of the thin film was selectively removed, and forming a contact plug by filling the contact hole with a conductive material.

摘要翻译： 一种制造半导体器件的方法，所述方法包括在衬底上形成包括栅极和源极和漏极区的晶体管，在所述晶体管上形成层间绝缘膜，在所述层间绝缘膜中形成接触孔以暴露出 源极和漏极区域的顶表面，并且在接触孔和源极和漏极区域的暴露顶表面之间的界面处形成薄膜。 该方法还包括通过在非等离子体气氛中进行蚀刻工艺来选择性地去除薄膜的至少一部分，在选择性地去除薄膜的至少一部分的源区和漏区上形成欧姆接触膜， 以及通过用导电材料填充接触孔来形成接触塞。

公开(公告)号：US20140231010A1

公开(公告)日：2014-08-21

申请号：US14183994

申请日：2014-02-19

申请人： Sang-Jine PARK ,  Bo-Un YOON ,  Jeong-Nam HAN ,  Kee-Sang KWON ,  Doo-Sung YUN ,  Won-Sang CHOI

发明人： Sang-Jine PARK ,  Bo-Un YOON ,  Jeong-Nam HAN ,  Kee-Sang KWON ,  Doo-Sung YUN ,  Won-Sang CHOI

IPC分类号： H01L21/67

CPC分类号： H01L21/67075 ,  H01L21/67017 ,  H01L21/6708

摘要： A chemical supplier includes a chemical reservoir containing a chemical mixture at a room temperature, an inner space of the chemical reservoir being separated from surroundings, a supply line through which the chemical mixture is supplied to a process chamber from the chemical reservoir, an inline heater positioned on the supply line and heating the chemical mixture in the supply line to a process temperature, and a power source driving the chemical mixture to move the chemical mixture toward the process chamber.

摘要翻译： 化学品供应商包括在室温下含有化学混合物的化学容器，化学容器的内部空间与周围环境分离，供应管线，化学混合物通过该供应管线从化学容器供应到处理室，一体式加热器 定位在供应管线上并将供应管线中的化学混合物加热至处理温度，以及驱动化学混合物以将化学混合物移向处理室的电源。

公开(公告)号：US20130012021A1

公开(公告)日：2013-01-10

申请号：US13526960

申请日：2012-06-19

申请人： Jung-Chan LEE ,  Yoo-Jung LEE ,  Ki-Hyung KO ,  Dae-Young KWAK ,  Seung-Jae LEE ,  Jae-Sung HUR ,  Sang-Bom KANG ,  Cheol KIM ,  Bo-Un YOON

发明人： Jung-Chan LEE ,  Yoo-Jung LEE ,  Ki-Hyung KO ,  Dae-Young KWAK ,  Seung-Jae LEE ,  Jae-Sung HUR ,  Sang-Bom KANG ,  Cheol KIM ,  Bo-Un YOON

IPC分类号： H01L21/283

CPC分类号： H01L29/4983 ,  H01L21/76895 ,  H01L21/82345 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/78

摘要： A method of manufacturing a semiconductor device includes forming an interlayer dielectric film that has first and second trenches on first and second regions of a substrate, respectively, forming a first metal layer along a sidewall and a bottom surface of the first trench and along a top surface of the interlayer dielectric film in the first region, forming a second metal layer along a sidewall and a bottom surface of the second trench and along a top surface of the interlayer dielectric film in the second region, forming a first sacrificial layer pattern on the first metal layer such that the first sacrificial layer fills a portion of the first trench, forming a first electrode layer by etching the first metal layer and the second metal layer using the first sacrificial layer pattern, and removing the first sacrificial layer pattern.

摘要翻译： 一种制造半导体器件的方法包括：在衬底的第一和第二区域上分别形成具有第一和第二沟槽的层间电介质膜，沿着第一沟槽的侧壁和底表面沿顶部形成第一金属层 在所述第一区域中的所述层间电介质膜的表面，沿着所述第二沟槽的侧壁和底表面沿着所述第二区域中的所述层间电介质膜的顶表面形成第二金属层，在所述第二区域中形成第一牺牲层图案 第一金属层，使得第一牺牲层填充第一沟槽的一部分，通过使用第一牺牲层图案蚀刻第一金属层和第二金属层形成第一电极层，以及去除第一牺牲层图案。

公开(公告)号：US20110124194A1

公开(公告)日：2011-05-26

申请号：US12953686

申请日：2010-11-24

申请人： Byoung-Ho KWON ,  Bo-Un YOON ,  Min-Sang KIM

发明人： Byoung-Ho KWON ,  Bo-Un YOON ,  Min-Sang KIM

IPC分类号： H01L21/302 ,  H01L21/306

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31053 ,  H01L21/76819 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device is provided. A pattern layer is formed on a substrate defined to include a main pattern region and a dummy pattern region. A preliminary main pattern and a preliminary dummy pattern may be formed by patterning the pattern layer so that an upper surface area of the preliminary dummy pattern facing away from a surface of the substrate is less than an entire area of the dummy pattern region that is be subjected to subsequent planarization. The preliminary main pattern and the preliminary dummy pattern are partially etched to form a main pattern and a dummy pattern.

摘要翻译： 提供一种制造半导体器件的方法。 在限定为包括主图案区域和虚设图案区域的基板上形成图案层。 可以通过图案化图案层来形成预备主图案和初步虚拟图案，使得预备虚拟图案的背离基板表面的上表面区域小于虚设图案区域的整个区域 进行随后的平面化。 部分蚀刻初步主图案和初步虚拟图案以形成主图案和虚拟图案。