公开(公告)号：US06703266B1

公开(公告)日：2004-03-09

申请号：US10249562

申请日：2003-04-18

申请人： Hsin-Ming Chen ,  Yaw-Ming Tsai ,  Chu-Jung Shih

发明人： Hsin-Ming Chen ,  Yaw-Ming Tsai ,  Chu-Jung Shih

IPC分类号： H01L2100

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/78621 ,  Y10S438/942

摘要： A method for fabricating a thin film transistor array and driving circuit comprising the steps of: providing a substrate; patterning a polysilicon layer and an N+ thin film over the substrate to form a plurality of islands; patterning the islands to form P+ doped regions; patterning out source/drain terminals and the lower electrode of a storage capacitor; etching back the N+ thin film; patterning out a gate and the upper electrode of the storage capacitor and patterning a passivation layer and a conductive layer to form pixel electrodes and a wiring layout.

摘要翻译： 一种制造薄膜晶体管阵列和驱动电路的方法，包括以下步骤：提供衬底; 在衬底上形成多晶硅层和N +薄膜以形成多个岛; 图案化岛以形成P +掺杂区域; 图案化存储电容器的源极/漏极端子和下部电极; 蚀刻N +薄膜; 图案化存储电容器的栅极和上电极，并且图案化钝化层和导电层以形成像素电极和布线布局。

公开(公告)号：US08787092B2

公开(公告)日：2014-07-22

申请号：US13418352

申请日：2012-03-13

申请人： Wei-Ren Chen ,  Te-Hsun Hsu ,  Hsin-Ming Chen

发明人： Wei-Ren Chen ,  Te-Hsun Hsu ,  Hsin-Ming Chen

IPC分类号： G11C16/04 ,  G11C16/10

CPC分类号： G11C16/10 ,  G11C16/0433

摘要： The invention provides a nonvolatile memory apparatus. The nonvolatile memory apparatus comprises a plurality of memory cells and a signal generator. The memory cells are arranged in an array, and each of the memory cells has a control gate terminal, a floating gate, a source line terminal, a bit-line terminal, a selected gate terminal and a word-line terminal. The signal generator is coupled to the memory cells. When the nonvolatile memory apparatus executes a programming operation, the signal generator provides a programming signal to the control gate terminals of a plurality of inhibited memory cells among the memory cells. Wherein, the programming signal is a pulse signal with a direct-current (DC) offset voltage.

摘要翻译： 本发明提供一种非易失性存储装置。 非易失性存储装置包括多个存储单元和信号发生器。 存储单元被布置成阵列，并且每个存储单元具有控制栅极端子，浮动栅极，源极线端子，位线端子，所选择的栅极端子和字线端子。 信号发生器耦合到存储单元。 当非易失性存储器件执行编程操作时，信号发生器向存储器单元中的多个禁止的存储单元的控制栅极端提供编程信号。 其中编程信号是具有直流（DC）偏移电压的脉冲信号。

公开(公告)号：US20130234228A1

公开(公告)日：2013-09-12

申请号：US13572731

申请日：2012-08-13

申请人： Te-Hsun Hsu ,  Hsin-Ming Chen ,  Ching-Sung Yang ,  Wen-Hao Ching ,  Wei-Ren Chen

发明人： Te-Hsun Hsu ,  Hsin-Ming Chen ,  Ching-Sung Yang ,  Wen-Hao Ching ,  Wei-Ren Chen

IPC分类号： H01L27/115

CPC分类号： H01L27/11558 ,  G11C16/0433 ,  G11C2216/10 ,  H01L29/42328 ,  H01L29/7883 ,  H01L29/7885

摘要： An erasable programmable single-poly nonvolatile memory includes a floating gate transistor having a floating gate, a gate oxide layer under the floating gate, and a channel region; and an erase gate region, wherein the floating gate is extended to and is adjacent to the erase gate region. The gate oxide layer comprises a first portion above the channel region of the floating gate transistor and a second portion above the erase gate region, and a thickness of the first portion of the gate oxide layer is different from a thickness of the second portion of the gate oxide layer.

摘要翻译： 可擦除可编程单一多晶硅非易失性存储器包括具有浮置栅极的浮栅晶体管，浮置栅极下方的栅极氧化物层和沟道区域; 和擦除栅极区，其中浮置栅极延伸到擦除栅极区并且与擦除栅极区相邻。 栅极氧化物层包括位于浮动栅极晶体管的沟道区上方的第一部分和擦除栅极区上方的第二部分，并且栅极氧化物层的第一部分的厚度与第二部分的厚度不同 栅氧化层。

公开(公告)号：US20130234227A1

公开(公告)日：2013-09-12

申请号：US13415185

申请日：2012-03-08

申请人： Wei-Ren Chen ,  Te-Hsun Hsu ,  Shih-Chen Wang ,  Hsin-Ming Chen ,  Ching-Sung Yang

发明人： Wei-Ren Chen ,  Te-Hsun Hsu ,  Shih-Chen Wang ,  Hsin-Ming Chen ,  Ching-Sung Yang

IPC分类号： H01L27/115

CPC分类号： H01L29/42328 ,  G11C16/0408 ,  H01L27/11558 ,  H01L29/7885

摘要： An erasable programmable single-poly nonvolatile memory includes a first PMOS transistor comprising a select gate, a first p-type doped region, and a second p-type doped region, wherein the select gate is connected to a select gate voltage, and the first p-type doped region is connected to a source line voltage; a second PMOS transistor comprising the second p-type doped region, a third p-type doped region, and a floating gate, wherein the third p-type doped region is connected to a bit line voltage; and an erase gate region adjacent to the floating gate, wherein the erase gate region is connected to an erase line voltage.

摘要翻译： 可擦除可编程单一多晶硅非易失性存储器包括包括选择栅极，第一p型掺杂区域和第二p型掺杂区域的第一PMOS晶体管，其中选择栅极连接到选择栅极电压，并且第一 p型掺杂区域连接到源极线电压; 包括第二p型掺杂区的第二PMOS晶体管，第三p型掺杂区和浮置栅，其中第三p型掺杂区连接到位线电压; 以及与浮置栅极相邻的擦除栅极区域，其中擦除栅极区域连接到擦除线电压。

公开(公告)号：US20120279124A1

公开(公告)日：2012-11-08

申请号：US13464031

申请日：2012-05-04

申请人： Hsin-Ming Chen

发明人： Hsin-Ming Chen

IPC分类号： A01G9/02

CPC分类号： A01G9/02

摘要： The present invention provides a versatile flower container includes a base, a top cover, a carrying container placing on the top of top cover and a sensing device placing in the base, the carrying container has a concave space can be used to accommodate the sponge, floral and water, the sensing device includes an electronic control panel, two humidity detection rod, a number of lamps and speakers, the two humidity detection rods are through the top cover and inserting into the sponge in the concave space, thereby they can detect the humidity values of the sponge, the lamps and the speaker can be activated to produce light and sound and then generate warning effect when the humidity values are not enough in the carrying container.

摘要翻译： 本发明提供了一种通用的花卉容器，其包括底座，顶盖，放置在顶盖顶部的承载容器和放置在基座中的感测装置，承载容器具有凹形空间可用于容纳海绵， 花卉和水，感应装置包括一个电子控制面板，两个湿度检测杆，多个灯和扬声器，两个湿度检测棒通过顶盖并插入到凹陷空间中的海绵中，从而可以检测到 海绵的湿度值，灯和扬声器可以被激活以产生光和声，并且当携带容器中的湿度值不足时产生警告效果。

公开(公告)号：US20120087170A1

公开(公告)日：2012-04-12

申请号：US12899562

申请日：2010-10-07

申请人： Hau-Yan Lu ,  Ching-Sung Yang ,  Shih-Chen Wang ,  Hsin-Ming Chen

发明人： Hau-Yan Lu ,  Ching-Sung Yang ,  Shih-Chen Wang ,  Hsin-Ming Chen

IPC分类号： G11C17/04 ,  G11C17/00

CPC分类号： G11C17/16 ,  G11C17/18

摘要： A one-time-programmable memory device comprises a one-time-programmable memory cell array, a voltage pumping circuit, and a programming verification circuit. The one-time-programmable memory cell array comprises a plurality of memory cells. Each memory cell is arranged at an intersection of a bit line and a word line. The voltage pumping circuit comprises a plurality of local voltage boost circuits. Each local voltage boost circuit is shared by a corresponding memory cell of the plurality of memory cells. The programming verification circuit is coupled to the one-time-programmable memory cell array for verifying that conduction current of programmed memory cells of the plurality of memory cells is greater than a predetermined current level after programming. Each local boost circuit isolates leakage current of a corresponding programmed memory cell, and prevents programming voltage failure due to current overloading at a corresponding voltage pumping circuit.

摘要翻译： 一次可编程存储器件包括一次可编程存储器单元阵列，电压泵浦电路和编程验证电路。 一次可编程存储单元阵列包括多个存储单元。 每个存储单元被布置在位线和字线的交点处。 电压泵浦电路包括多个局部升压电路。 每个本地升压电路由多个存储单元的相应存储单元共享。 编程验证电路耦合到一次可编程存储单元阵列，用于在编程之后验证多个存储单元的编程存储单元的传导电流大于预定电流电平。 每个本地升压电路隔离相应的编程存储单元的漏电流，并且防止由于在相应的电压泵浦电路处的电流过载导致的编程电压故障。

公开(公告)号：US20110057243A1

公开(公告)日：2011-03-10

申请号：US12943945

申请日：2010-11-11

申请人： Hsin-Ming Chen ,  Hai-Ming Lee ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

发明人： Hsin-Ming Chen ,  Hai-Ming Lee ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

IPC分类号： H01L27/12

CPC分类号： H01L27/115

摘要： A non-volatile memory disposed in a SOI substrate is provided. The non-volatile memory includes a memory cell and a first conductive type doped region. The memory cell includes a gate, a charge storage structure, a bottom dielectric layer, a second conductive type drain region, and a second conductive type source region. The gate is disposed on the SOI substrate. The charge storage structure is disposed between the gate and the SOI substrate. The bottom dielectric layer is disposed between the charge storage layer and the SOI substrate. The second conductive type drain region and the second conductive type source region are disposed in a first conductive type silicon body layer next to the two sides of the gate. The first conductive type doped region is disposed in the first conductive type silicon body layer and electrically connected to the first conductive type silicon body layer beneath the gate.

摘要翻译： 设置在SOI衬底中的非易失性存储器。 非易失性存储器包括存储单元和第一导电类型掺杂区域。 存储单元包括栅极，电荷存储结构，底部电介质层，第二导电类型漏极区域和第二导电型源极区域。 栅极设置在SOI衬底上。 电荷存储结构设置在栅极和SOI衬底之间。 底部电介质层设置在电荷存储层和SOI衬底之间。 第二导电型漏极区域和第二导电型源极区域设置在栅极的两侧旁边的第一导电型硅体层中。 第一导电型掺杂区域设置在第一导电型硅体层中，并且与栅极下方的第一导电型硅体层电连接。

公开(公告)号：US20070296034A1

公开(公告)日：2007-12-27

申请号：US11759949

申请日：2007-06-08

申请人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Ming-Chou Ho ,  Shih-Jye Shen

发明人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Ming-Chou Ho ,  Shih-Jye Shen

IPC分类号： H01L27/12

CPC分类号： H01L27/1203 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11558

摘要： A single-poly SOI memory cell includes a PMOS select transistor serially connected with a floating-gate PMOS transistor on an SOI substrate. The PMOS select transistor includes a select gate, a P+ source region and a P+ drain/source region. The floating-gate PMOS transistor includes a floating gate, a P+ drain region and the P+ drain/source region, wherein the P+ drain/source region is shared by the PMOS select transistor and the floating-gate PMOS transistor. A floating first N+ doping region is disposed within the P+ drain/source region. The first N+ doping region, which is adjacent to the floating gate, acts as a source-tie pick-up.

摘要翻译： 单多晶硅存储单元包括与SOI衬底上的浮栅PMOS晶体管串联连接的PMOS选择晶体管。 PMOS选择晶体管包括选择栅极，P + SUP源极区和P + SUP漏极/源极区。 浮置栅极PMOS晶体管包括浮置栅极，漏极和漏极区域，其中P + 漏极/源极区域由PMOS选择晶体管和浮置栅极PMOS晶体管共享。 漂浮的第一N + +掺杂区域设置在漏极/源极区域内。 与浮动栅极相邻的第一N + H + +掺杂区充当源极接头。

公开(公告)号：US20070296018A1

公开(公告)日：2007-12-27

申请号：US11690861

申请日：2007-03-26

申请人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Ming-Chou Ho ,  Shih-Jye Shen

发明人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Ming-Chou Ho ,  Shih-Jye Shen

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11558

摘要： A non-volatile single-poly memory device is disclosed. The non-volatile single-poly memory device includes two mirror symmetric unit cells, which is capable of providing improved data correctness. Further, the non-volatile single-poly memory device is operated at low voltages and is fully compatible with logic processes.

摘要翻译： 公开了一种非易失性单多晶硅存储器件。 非易失性单多晶硅存储器件包括两个镜像对称单元单元，其能够提供改进的数据正确性。 此外，非易失性单多晶硅存储器件在低电压下操作并且与逻辑工艺完全兼容。

公开(公告)号：US20070111357A1

公开(公告)日：2007-05-17

申请号：US11557111

申请日：2006-11-07

申请人： Shih-Chen Wang ,  Hsin-Ming Chen ,  Chun-Hung Lu ,  Ming-Chou Ho ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

发明人： Shih-Chen Wang ,  Hsin-Ming Chen ,  Chun-Hung Lu ,  Ming-Chou Ho ,  Shih-Jye Shen ,  Ching-Hsiang Hsu

IPC分类号： H01L21/00

CPC分类号： G11C16/0475 ,  G11C16/0425 ,  G11C16/0466 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7835 ,  H01L29/7887 ,  H01L29/792 ,  H01L29/7923

摘要： A non-volatile memory formed on a first conductive type substrate is provided. The non-volatile memory includes a gate, a second conductive type drain region, a charge storage layer, and a second conductive type first lightly doped region. The gate is formed on the first conductive type substrate. The second conductive type drain region is formed in the first conductive type substrate at the first side of the gate. The charge storage layer is formed on the first conductive type substrate at the first side of the gate and between the second conductive type drain region and the gate. The second conductive type first lightly doped region is formed in the first conductive type substrate at the second side of the gate. The second side is opposite to the first side.

摘要翻译： 提供了形成在第一导电型基板上的非易失性存储器。 非易失性存储器包括栅极，第二导电型漏极区，电荷存储层和第二导电型第一轻掺杂区域。 栅极形成在第一导电类型的基板上。 第二导电型漏极区域形成在栅极的第一侧的第一导电型衬底中。 电荷存储层形成在栅极的第一侧的第一导电型基板和第二导电型漏极区域与栅极之间。 第二导电型第一轻掺杂区域形成在栅极第二侧的第一导电型衬底中。 第二面与第一面相反。