SYSTEMS AND METHODS FOR HORIZONTAL INTEGRATION OF ACCELERATION SENSOR STRUCTURES
    2.
    发明申请
    SYSTEMS AND METHODS FOR HORIZONTAL INTEGRATION OF ACCELERATION SENSOR STRUCTURES 审中-公开
    用于加速传感器结构的水平积分的系统和方法

    公开(公告)号:US20160185594A1

    公开(公告)日:2016-06-30

    申请号:US15064916

    申请日:2016-03-09

    Abstract: Embodiments relate to integrated circuit sensors, and more particularly to sensors integrated in an integrated circuit structure and methods for producing the sensors. In an embodiment, a sensor device comprises a substrate; a first trench in the substrate; a first moveable element suspended in the first trench by a first plurality of support elements spaced apart from one another and arranged at a perimeter of the first moveable element; and a first layer arranged on the substrate to seal the first trench, thereby providing a first cavity containing the first moveable element and the first plurality of support elements.

    Abstract translation: 实施例涉及集成电路传感器,更具体地涉及集成在集成电路结构中的传感器和用于产生传感器的方法。 在一个实施例中,传感器装置包括衬底; 衬底中的第一沟槽; 第一可移动元件,其通过彼此间隔开并布置在第一可移动元件的周边的第一多个支撑元件悬挂在第一沟槽中; 以及布置在所述基板上以密封所述第一沟槽的第一层,从而提供包含所述第一可移动元件和所述第一多个支撑元件的第一空腔。

    Method and structure for creating cavities with extreme aspect ratios
    6.
    发明授权
    Method and structure for creating cavities with extreme aspect ratios 有权
    用于创建具有极高宽比的腔体的方法和结构

    公开(公告)号:US09136136B2

    公开(公告)日:2015-09-15

    申请号:US14031694

    申请日:2013-09-19

    Abstract: Embodiments relate to structures, systems and methods for more efficiently and effectively etching sacrificial and other layers in substrates and other structures. In embodiments, a substrate in which a sacrificial layer is to be removed to, e.g., form a cavity comprises an etch dispersion system comprising a trench, channel or other structure in which etch gas or another suitable gas, fluid or substance can flow to penetrate the substrate and remove the sacrificial layer. The trench, channel or other structure can be implemented along with openings or other apertures formed in the substrate, such as proximate one or more edges of the substrate, to even more quickly disperse etch gas or some other substance within the substrate.

    Abstract translation: 实施例涉及用于更有效地和有效地蚀刻衬底和其它结构中的牺牲层和其它层的结构,系统和方法。 在实施例中,其中牺牲层被去除以例如形成空腔的衬底包括蚀刻分散体系统,其包括沟槽,沟道或其它结构,其中蚀刻气体或其它合适的气体,流体或物质可以流过其中 衬底并去除牺牲层。 沟槽,沟道或其它结构可以与形成在衬底中的开口或其他孔一起实现,例如靠近衬底的一个或多个边缘,以更快地将蚀刻气体或一些其它物质分散在衬底内。

    METHOD AND STRUCTURE FOR CREATING CAVITIES WITH EXTREME ASPECT RATIOS
    7.
    发明申请
    METHOD AND STRUCTURE FOR CREATING CAVITIES WITH EXTREME ASPECT RATIOS 有权
    用极端的方法创建CAVIITY的方法和结构

    公开(公告)号:US20150079787A1

    公开(公告)日:2015-03-19

    申请号:US14031694

    申请日:2013-09-19

    Abstract: Embodiments relate to structures, systems and methods for more efficiently and effectively etching sacrificial and other layers in substrates and other structures. In embodiments, a substrate in which a sacrificial layer is to be removed to, e.g., form a cavity comprises an etch dispersion system comprising a trench, channel or other structure in which etch gas or another suitable gas, fluid or substance can flow to penetrate the substrate and remove the sacrificial layer. The trench, channel or other structure can be implemented along with openings or other apertures formed in the substrate, such as proximate one or more edges of the substrate, to even more quickly disperse etch gas or some other substance within the substrate.

    Abstract translation: 实施例涉及用于更有效地和有效地蚀刻衬底和其它结构中的牺牲层和其它层的结构,系统和方法。 在实施例中,其中牺牲层被去除以例如形成空腔的衬底包括蚀刻分散体系统,其包括沟槽,沟道或其它结构,其中蚀刻气体或其它合适的气体,流体或物质可以流过其中 衬底并去除牺牲层。 沟槽,沟道或其它结构可以与形成在衬底中的开口或其他孔一起实现,例如靠近衬底的一个或多个边缘,以更快地将蚀刻气体或一些其它物质分散在衬底内。

    Contact Hole
    10.
    发明申请
    Contact Hole 审中-公开

    公开(公告)号:US20190189509A1

    公开(公告)日:2019-06-20

    申请号:US16225423

    申请日:2018-12-19

    CPC classification number: H01L21/76877 H01L21/28556 H01L21/76853

    Abstract: A power semiconductor component includes a power semiconductor partial structure having an insulating layer arranged on an upper side of a semiconductor body. A contact hole arranged on an upper side of the insulating layer proceeds from that side, extending at least partly within the insulating layer. An adhesion promoter layer arranged on an upper side of the power semiconductor partial structure at least partly covers the insulating layer upper side and a surface of the contact hole. A tungsten-comprising layer arranged on the adhesion promoter layer at least partly covers the adhesion promoter layer and has a first thickness in a region of the contact hole and dimensioned such that the tungsten-comprising layer fills the contact hole. The tungsten-comprising layer has a second thickness in the region of the insulating layer upper side which is less than the first thickness. A connection layer is arranged on the tungsten-comprising layer.

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