公开(公告)号：US11489112B2

公开(公告)日：2022-11-01

申请号：US16641582

申请日：2017-09-28

Applicant: INTEL CORPORATION

Inventor： Namrata S. Asuri ,  Oleg Golonzka ,  Nathan Strutt ,  Patrick J. Hentges ,  Trinh T. Van ,  Hiten Kothari ,  Ameya S. Chaudhari ,  Matthew J. Andrus ,  Timothy E. Glassman ,  Dragos Seghete ,  Christopher J. Wiegand ,  Daniel G. Ouellette

IPC: H01L45/00 ,  H01L23/528 ,  H01L27/24

Abstract: An apparatus, includes an interconnect, including a conductive material, above a substrate and a resistive random access memory (RRAM) device coupled to the interconnect. The RRAM device includes an electrode structure above the interconnect, where an upper portion of the electrode structure has a first width. The RRAM device further includes a switching layer on the electrode structure, where the switching layer has the first width and an oxygen exchange layer, having a second width less than the first width, on a portion of the switching layer. The RRAM device further includes a top electrode above the oxygen exchange layer, where the top electrode has the second width and an encapsulation layer on a portion of the switching layer, where the switching layer extends along a sidewall of the oxygen exchange layer.

公开(公告)号：US11430948B2

公开(公告)日：2022-08-30

申请号：US16641588

申请日：2017-09-28

Applicant: INTEL CORPORATION

Inventor： Timothy Glassman ,  Dragos Seghete ,  Nathan Strutt ,  Namrata S. Asuri ,  Oleg Golonzka ,  Hiten Kothari ,  Matthew J. Andrus

IPC: H01L45/00 ,  H01L27/24

Abstract: A memory device includes a bottom electrode above a substrate, a first switching layer on the bottom electrode, a second switching layer including aluminum on the first switching layer, an oxygen exchange layer on the second switching layer and a top electrode on the oxygen exchange layer. The presence of the second switching layer including aluminum on the first switching layer enables a reduction in electro-forming voltage of the memory device.

公开(公告)号：US09818710B2

公开(公告)日：2017-11-14

申请号：US15120788

申请日：2014-03-28

Applicant: Intel Corporation

Inventor： Jiho Kang ,  Hiten Kothari ,  Carole C. Montarou ,  Andrew W. Yeoh

IPC: H01L23/00 ,  H01L23/31

CPC classification number: H01L24/13 ,  H01L23/291 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/03831 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13184 ,  H01L2924/35121 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: An embodiment includes a semiconductor structure comprising: a backend portion including a plurality of metal layers between bottom and top metal layers; the top metal layer including a top metal layer portion having first and second opposing sidewall surfaces and a top surface that couples the sidewall surfaces to one another; an insulator layer directly contacting the top surface; and a via coupling a contact bump to the top metal layer portion; wherein a first vertical axis, orthogonal to a substrate coupled to the backend portion, intercepts the contact bump, the nitride layer, the via, and the top metal layer portion. Other embodiments are described herein.

公开(公告)号：US09721886B2

公开(公告)日：2017-08-01

申请号：US14778667

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： Kevin J. Lee ,  Hiten Kothari ,  Wayne M. Lytle

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L23/525 ,  H01L23/48

CPC classification number: H01L23/528 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76885 ,  H01L23/481 ,  H01L23/525 ,  H01L23/53238 ,  H01L2224/1182 ,  H01L2224/13565

Abstract: An embodiment includes a semiconductor apparatus comprising: a redistribution layer (RDL) including a patterned RDL line having two RDL sidewalls, the RDL comprising a material selected from the group comprising Cu and Au; protective sidewalls directly contacting the two RDL sidewalls; a seed layer including the material; and a barrier layer; wherein (a) the RDL line has a RDL line width orthogonal to and extending between the two RDL sidewalls, and (b) the seed and barrier layers each include a width parallel to and wider than the RDL line width. Other embodiments are described herein.

公开(公告)号：US09530740B2

公开(公告)日：2016-12-27

申请号：US14836828

申请日：2015-08-26

Applicant: Intel Corporation

Inventor： Kevin J. Lee ,  Mark T. Bohr ,  Andrew W. Yeoh ,  Christopher M. Pelto ,  Hiten Kothari ,  Seshu V. Sattiraju ,  Hang-Shing Ma

IPC: H01L23/48 ,  H01L23/538 ,  H01L21/768 ,  H01L23/00 ,  H01L23/522 ,  H01L23/29 ,  H01L23/31 ,  H01L23/528 ,  H01L21/683

CPC classification number: H01L23/5384 ,  H01L21/6835 ,  H01L21/76807 ,  H01L21/76898 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5286 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/13 ,  H01L24/17 ,  H01L2221/6835 ,  H01L2224/0235 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17106 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/186 ,  H01L2924/381 ,  H01L2924/01015 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A 3D interconnect structure and method of manufacture are described in which a through-silicon vias (TSVs) and metal redistribution layers (RDLs) are formed using a dual damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and etch stop layer during the process flow.