公开(公告)号：US11715928B2

公开(公告)日：2023-08-01

申请号：US16554789

申请日：2019-08-29

Applicant: INTEL CORPORATION

Inventor： Priyanka Dobriyal ,  Susheel G. Jadhav ,  Ankur Agrawal ,  Quan A. Tran ,  Raiyomand F. Aspandiar ,  Kenneth M. Brown

IPC: H01S5/0234 ,  G02F1/015 ,  H01S5/0237 ,  H01S5/02234 ,  H01S5/02325 ,  H01S5/026

CPC classification number: H01S5/0234 ,  G02F1/015 ,  H01S5/0237 ,  H01S5/02234 ,  H01S5/02325 ,  H01S5/0261

Abstract: An integrated circuit assembly includes a support (e.g., package substrate or circuit board) and a semiconductor die including a device. The semiconductor die is mounted to the support with the device facing the support. The device can be, for example, a quantum well laser device or a photonics device. A layer of decoupling material is on the device. An underfill material is between the semiconductor die and the support, where the decoupling material is between the device and the underfill material. The decoupling layer decouples stress from transferring from the underfill material into the device. For example, the decoupling material forms only weak bonds with the underfill material and/or a passivation layer on the device, in an embodiment. Weak bonds include non-covalent bonds and non-ionic bonds, for example. The decoupling material can be, for instance, a PTFE film, a poly(p-xylylene) film, a fluorocarbon, or a compound lacking free hydroxyl groups.

公开(公告)号：US20170288780A1

公开(公告)日：2017-10-05

申请号：US15087344

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Myung Jin Yim ,  Quan A. Tran ,  SeungJae Lee ,  Sandeep Razdan ,  Yigit O. Yilmaz ,  Pradeep Srinivasan ,  Jincheng Wang ,  Ansheng Liu

IPC: H04B10/50 ,  H01S3/10 ,  H01S3/02 ,  H01S3/23

CPC classification number: H04B10/503 ,  H01L2224/73204 ,  H01S3/2375 ,  H01S5/021 ,  H01S5/02248 ,  H01S5/4087

Abstract: Apparatuses including integrated circuit (IC) optical assemblies and processes for fabrication of IC optical assemblies are disclosed herein. In some embodiments, the IC optical assemblies include an optical transmitter component electrically coupled to a first portion of a packaging substrate. The IC optical assemblies further include an optical transmitter driver component between the optical transmitter component and a second portion of the packaging substrate, wherein a first side of the optical transmitter driver component is electrically coupled to the optical transmitter component. The IC optical assemblies further include a plurality of bumps between a second side of the optical transmitter driver component and proximate the second portion of the packaging substrate, wherein the plurality of bumps are not directly coupled to the optical transmitter driver component.

公开(公告)号：US20210066882A1

公开(公告)日：2021-03-04

申请号：US16554789

申请日：2019-08-29

Applicant: INTEL CORPORATION

Inventor： Priyanka Dobriyal ,  Susheel G. Jadhav ,  Ankur Agrawal ,  Quan A. Tran ,  Raiyomand F. Aspandiar ,  Kenneth M. Brown

IPC: H01S5/022 ,  G02F1/015

Abstract: An integrated circuit assembly includes a support (e.g., package substrate or circuit board) and a semiconductor die including a device. The semiconductor die is mounted to the support with the device facing the support. The device can be, for example, a quantum well laser device or a photonics device. A layer of decoupling material is on the device. An underfill material is between the semiconductor die and the support, where the decoupling material is between the device and the underfill material. The decoupling layer decouples stress from transferring from the underfill material into the device. For example, the decoupling material forms only weak bonds with the underfill material and/or a passivation layer on the device, in an embodiment. Weak bonds include non-covalent bonds and non-ionic bonds, for example. The decoupling material can be, for instance, a PTFE film, a poly(p-xylylene) film, a fluorocarbon, or a compound lacking free hydroxyl groups.

公开(公告)号：US09686861B2

公开(公告)日：2017-06-20

申请号：US15172029

申请日：2016-06-02

Applicant: Intel Corporation

Inventor： Qing Ma ,  Quan A. Tran ,  Robert L. Sankman ,  Johanna M. Swan ,  Valluri R. Rao

IPC: H05K1/11 ,  H01L21/48 ,  H01L23/367 ,  H01L23/498 ,  H05K3/46 ,  H01L23/15 ,  H05K3/00

CPC classification number: H05K1/112 ,  H01L21/4803 ,  H01L21/486 ,  H01L23/15 ,  H01L23/3675 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/10253 ,  H05K3/0014 ,  H05K3/4605 ,  H05K3/4644 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2201/10287 ,  H05K2201/10371 ,  H05K2201/10674 ,  H05K2203/0108 ,  H05K2203/0228 ,  H05K2203/025 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2224/0401

Abstract: Disclosed are embodiments of a glass core substrate for an integrated circuit (IC) device. The glass core substrate includes a glass core and build-up structures on opposing sides of the glass core. Electrically conductive terminals may be formed on both sides of the glass core substrate. An IC die may be coupled with the terminals on one side of the substrate, whereas the terminals on the opposing side may be coupled with a next-level component, such as a circuit board. The glass core may comprise a single piece of glass in which conductors have been formed, or the glass core may comprise two or more glass sections that have been joined together, each section having conductors. The conductors extend through the glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the glass core. Other embodiments are described and claimed.