公开(公告)号：US10403602B2

公开(公告)日：2019-09-03

申请号：US15637935

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Georg Seidemann ,  Andreas Augustin ,  Laurent Millou ,  Andreas Wolter ,  Reinhard Mahnkopf ,  Stephan Stoeckl ,  Thomas Wagner

IPC: H01L21/48 ,  H01L25/065 ,  H01L23/48 ,  G06F15/76 ,  H01L25/00

Abstract: A semiconductive device stack, includes a baseband processor die with an active surface and a backside surface, and a recess in the backside surface. A recess-seated device is disposed in the recess, and a through-silicon via in the baseband processor die couples the baseband processor die at the active surface to the recess-seated die at the recess. A processor die is disposed on the baseband processor die backside surface, and a memory die is disposed on the processor die. The several dice are coupled by through-silicon via groups.

公开(公告)号：US11764187B2

公开(公告)日：2023-09-19

申请号：US16641241

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Georg Seidemann ,  Thomas Wagner ,  Andreas Wolter ,  Andreas Augustin ,  Sonja Koller ,  Thomas Ort ,  Reinhard Mahnkopf

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2225/0651 ,  H01L2225/06506 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06586

Abstract: A semiconductor package includes a first semiconductor die, a semiconductor device comprising a second semiconductor die, and one or more wire bond structures. The wire bond structure includes a bond interface portion. The wire bond structure is arranged next to the first semiconductor die. The first semiconductor die and the bond interface portion of the wire bond structure are arranged at the same side of the semiconductor device. An interface contact structure of the semiconductor device is electrically connected to the wire bond structure.

公开(公告)号：US09564400B2

公开(公告)日：2017-02-07

申请号：US15009731

申请日：2016-01-28

Applicant: Intel Corporation

Inventor： Reinhard Mahnkopf ,  Wolfgang Molzer ,  Bernd Memmler ,  Edmund Goetz ,  Hans-Joachim Barth ,  Sven Albers ,  Thorsten Meyer

IPC: H01L21/44 ,  H01L23/538 ,  H01L21/768 ,  H01L23/522 ,  H01L23/00 ,  H01L25/07 ,  H01L25/00 ,  H01L25/065 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/5389 ,  H01L21/56 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/3121 ,  H01L23/5226 ,  H01L23/5384 ,  H01L23/562 ,  H01L24/03 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/50 ,  H01L2224/08146 ,  H01L2224/16148 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Embodiments of the present description include stacked microelectronic dice embedded in a microelectronic substrate and methods of fabricating the same. In one embodiment, at least one first microelectronic die is attached to a second microelectronic die, wherein an underfill material is provided between the second microelectronic die and the at least one first microelectronic die. The microelectronic substrate is then formed by laminating the first microelectronic die and the second microelectronic die in a substrate material.

Abstract translation: 本说明书的实施例包括嵌入在微电子衬底中的堆叠微电子骰子及其制造方法。 在一个实施例中，至少一个第一微电子管芯连接到第二微电子管芯，其中在第二微电子管芯和至少一个第一微电子管芯之间提供底部填充材料。 然后通过将第一微电子管芯和第二微电子管芯层压在衬底材料中来形成微电子衬底。

公开(公告)号：US11456116B2

公开(公告)日：2022-09-27

申请号：US16474015

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Andreas Augustin ,  Bernd Waidhas ,  Sonja Koller ,  Reinhard Mahnkopf ,  Georg Seidemann

IPC: H01F27/24 ,  H01F41/04 ,  H01F17/00 ,  H01L23/64 ,  H01L27/01 ,  H01L49/02

Abstract: A recess in a die backside surface occupies a footprint that accommodates an inductor coil that is formed in metallization above an active surface of the die. Less semiconductive material is therefore close to the inductor coil. A ferromagnetic material is formed in the recess, or a ferromagnetic material is formed on a dielectric layer above the inductor coil. The recess may extend across a die that allows the die to be deflected at the recess.

公开(公告)号：US09888577B2

公开(公告)日：2018-02-06

申请号：US14229476

申请日：2014-03-28

Applicant: INTEL CORPORATION

Inventor： Thorsten Meyer ,  Gerald Ofner ,  Sven Albers ,  Reinhard Mahnkopf

IPC: H05K1/18 ,  H01L23/498 ,  H01L23/522 ,  H01L23/66 ,  H05K1/02 ,  H01L23/00 ,  H05K1/16 ,  H05K3/46 ,  H01L21/56 ,  H01L25/065 ,  H01L25/16 ,  H01L25/18

CPC classification number: H05K1/181 ,  H01L21/568 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5227 ,  H01L23/66 ,  H01L24/00 ,  H01L24/96 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/04042 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/19011 ,  H01L2924/19105 ,  H05K1/0233 ,  H05K1/0292 ,  H05K1/162 ,  H05K1/165 ,  H05K1/185 ,  H05K3/4644 ,  H05K2201/10636 ,  H05K2203/1469 ,  H05K2203/171 ,  H05K2203/173 ,  H05K2203/175 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Passive electrical devices are described with a polymer carrier. In one example, a conductive layer is formed over a polymer substrate in a pattern to form a passive electrical device and at least two terminals of the device. A plurality of external connection pads are connected to the terminals of the device.

公开(公告)号：US20190006318A1

公开(公告)日：2019-01-03

申请号：US15637935

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Georg Seidemann ,  Andreas Augustin ,  Laurent Millou ,  Andreas Wolter ,  Reinhard Mahnkopf ,  Stephan Stoeckl ,  Thomas Wagner

IPC: H01L25/065 ,  H01L21/48 ,  H01L23/48

CPC classification number: H01L25/0657 ,  G06F15/76 ,  H01L21/486 ,  H01L23/481 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/1011 ,  H01L2225/1017 ,  H01L2225/1058

Abstract: A semiconductive device stack, includes a baseband processor die with an active surface and a backside surface, and a recess in the backside surface. A recess-seated device is disposed in the recess, and a through-silicon via in the baseband processor die couples the baseband processor die at the active surface to the recess-seated die at the recess. A processor die is disposed on the baseband processor die backside surface, and a memory die is disposed on the processor die. The several dice are coupled by through-silicon via groups.

公开(公告)号：US20160148920A1

公开(公告)日：2016-05-26

申请号：US15009731

申请日：2016-01-28

Applicant: Intel Corporation

Inventor： Reinhard Mahnkopf ,  Wolfgang Molzer ,  Bernd Memmler ,  Edmund Goetz ,  Hans-Joachim Barth ,  Sven Albers ,  Thorsten Meyer

IPC: H01L25/00 ,  H01L21/768 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/5389 ,  H01L21/56 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/3121 ,  H01L23/5226 ,  H01L23/5384 ,  H01L23/562 ,  H01L24/03 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/50 ,  H01L2224/08146 ,  H01L2224/16148 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Embodiments of the present description include stacked microelectronic dice embedded in a microelectronic substrate and methods of fabricating the same. In one embodiment, at least one first microelectronic die is attached to a second microelectronic die, wherein an underfill material is provided between the second microelectronic die and the at least one first microelectronic die. The microelectronic substrate is then formed by laminating the first microelectronic die and the second microelectronic die in a substrate material.

公开(公告)号：US09373588B2

公开(公告)日：2016-06-21

申请号：US14034854

申请日：2013-09-24

Applicant: Intel Corporation

Inventor： Reinhard Mahnkopf ,  Wolfgang Molzer ,  Bernd Memmler ,  Edmund Goetz ,  Hans-Joachim Barth ,  Sven Albers ,  Thorsten Meyer

IPC: H01L29/40 ,  H01L23/538 ,  H01L21/768 ,  H01L23/522 ,  H01L23/00 ,  H01L25/07 ,  H01L25/00 ,  H01L25/065 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/5389 ,  H01L21/56 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/3121 ,  H01L23/5226 ,  H01L23/5384 ,  H01L23/562 ,  H01L24/03 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/50 ,  H01L2224/08146 ,  H01L2224/16148 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Embodiments of the present description include stacked microelectronic dice embedded in a microelectronic substrate and methods of fabricating the same. In one embodiment, at least one first microelectronic die is attached to a second microelectronic die, wherein an underfill material is provided between the second microelectronic die and the at least one first microelectronic die. The microelectronic substrate is then formed by laminating the first microelectronic die and the second microelectronic die in a substrate material.

Abstract translation: 本说明书的实施例包括嵌入在微电子衬底中的堆叠微电子骰子及其制造方法。 在一个实施例中，至少一个第一微电子管芯连接到第二微电子管芯，其中在第二微电子管芯和至少一个第一微电子管芯之间提供底部填充材料。 然后通过将第一微电子管芯和第二微电子管芯层压在衬底材料中来形成微电子衬底。