公开(公告)号：US12266581B2

公开(公告)日：2025-04-01

申请号：US17085177

申请日：2020-10-30

Applicant: Intel Corporation

Inventor： Joshua Stacey ,  Whitney Bryks ,  Sarah Blythe ,  Peumie Abeyratne Kuragama ,  Junxin Wang

IPC: H01L23/18 ,  H01L23/29 ,  H01L23/31 ,  H01L23/522

Abstract: An electronic substrate may be formed having at least one dielectric layer that is heterogeneous. The heterogeneous dielectric layer may comprise three separately formed materials that decouple the critical regions within a dielectric layer and allow for the optimization of desired interfacial properties, while minimizing the impact to the bulk requirements of the electronic substrate.

公开(公告)号：US20240222211A1

公开(公告)日：2024-07-04

申请号：US18091270

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Peumie Abeyratne Kuragama ,  Dilan Seneviratne ,  Whitney Bryks

IPC: H01L23/16 ,  H01L23/00 ,  H01L23/15 ,  H01L23/538

CPC classification number: H01L23/16 ,  H01L23/15 ,  H01L23/5383 ,  H01L23/562

Abstract: IC device packages including a low-CTE polymer dielectric build-up material comprising a filler having a negative CTE. Low CTE build-up materials may have a CTE less than 10 ppm/K below the glass transition temperature (Tg) of the polymer resin containing the filler. With a negative CTE filler, polymer resin expansion during thermal cycles (e.g., resin cure) may be at least partially countered through negative thermal expansion of the filler.

公开(公告)号：US20250125202A1

公开(公告)日：2025-04-17

申请号：US18984444

申请日：2024-12-17

Applicant: Intel Corporation

Inventor： Brandon Christian Marin ,  Whitney Bryks ,  Gang Duan ,  Jeremy Ecton ,  Jason Gamba ,  Haifa Hariri ,  Sashi Shekhar Kandanur ,  Joseph Peoples ,  Srinivas Venkata Ramanuja Pietambaram ,  Mohammad Mamunur Rahman ,  Bohan Shan ,  Joshua James Stacey ,  Hiroki Tanaka ,  Jacob Ryan Vehonsky

IPC: H01L23/15 ,  H01L23/18 ,  H01L23/498 ,  H01L23/64

Abstract: Package substrates with components included in cavities of glass cores are disclosed. An example apparatus includes: a glass layer having an opening between opposing first and second surfaces of the glass layer; an electronic component within the opening; a dielectric material within the opening between the electronic component and a sidewall of the opening; and a through-glass via including a conductive material that extends through the glass layer.

公开(公告)号：US20240096561A1

公开(公告)日：2024-03-21

申请号：US17948586

申请日：2022-09-20

Applicant: Intel Corporation

Inventor： Mahdi Mohammadighaleni ,  Benjamin Duong ,  Shayan Kaviani ,  Joshua Stacey ,  Miranda Ngan ,  Dilan Seneviratne ,  Thomas Heaton ,  Srinivas Venkata Ramanuja Pietambaram ,  Whitney Bryks ,  Jieying Kong

IPC: H01G4/33 ,  H01G4/012

CPC classification number: H01G4/33 ,  H01G4/012 ,  H01L28/92 ,  H01L25/16

Abstract: An apparatus, system, and method for in-situ three-dimensional (3D) thin-film capacitor (TFC) are provided. A 3D TFC can include a glass core, a through glass via (TGV) in the glass core including first conductive material, the first conductive material forming a first electrode of the 3D MIM capacitor, a second conductive material acting as a second electrode of the 3D MIM capacitor, and a dielectric material in contact with the first and second conductive materials, the dielectric material extending vertically and horizontally and physically separating the first and second conductive materials.

公开(公告)号：US11296186B2

公开(公告)日：2022-04-05

申请号：US16737680

申请日：2020-01-08

Applicant: Intel Corporation

Inventor： Brandon C Marin ,  Praneeth Akkinepally ,  Whitney Bryks ,  Dilan Seneviratne ,  Frank Truong

IPC: H01L23/532 ,  H01L49/02 ,  H01L21/768 ,  H01L23/00

Abstract: Disclosed embodiments include in-recess fabricated vertical capacitor cells, that can be assembled as close to the surface of a semiconductor package substrate as the first-level interconnect surface. The in-recess fabricated vertical capacitor cells are semiconductor package-integrated capacitors. Disclosed embodiments include laminated vertical capacitor cells where a plated through-hole is twice breached to form opposing capacitor plates. The breached, plated through-hole capacitors are semiconductor package-integrated capacitors.

公开(公告)号：US20250112163A1

公开(公告)日：2025-04-03

申请号：US18375203

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Pratyush Mishra ,  Pratyasha Mohapatra ,  Srinivas Pietambaram ,  Whitney Bryks ,  Mahdi Mohammadighaleni ,  Joshua Stacey ,  Travis Palmer ,  Yosef Kornbluth ,  Kuang Liu ,  Astitva Tripathi ,  Yuqin Li ,  Rengarajan Shanmugam ,  Xing Sun ,  Brian Balch ,  Darko Grujicic ,  Jieying Kong ,  Nicholas Haehn ,  Jacob Vehonsky ,  Mitchell Page ,  Vincent Obiozo Eze ,  Daniel Wandera ,  Sameer Paital ,  Gang Duan

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/15 ,  H01L25/065

Abstract: An IC die package includes a substrate comprising glass and a plurality of holes extending through the glass. A via metallization is present within the holes. A liner is between the via metallization and the glass. The liner can comprise a beta-titanium alloy layer, polymer hydrogel layer and an MXene seed layer, an organic material layer and a metal layer, or an organic material layer between first and second metal layers. A polymer layer may be formed by electrodeposition of charged nanoparticles.

公开(公告)号：US12214579B2

公开(公告)日：2025-02-04

申请号：US17949276

申请日：2022-09-21

Applicant: Intel Corporation

Inventor： Joshua Stacey ,  Yosef Kornbluth ,  Whitney Bryks

IPC: B32B41/00 ,  B32B37/06 ,  B32B37/08 ,  B32B37/10 ,  H01L21/48

Abstract: The present disclosure is directed to a position-controlled lamination tool or press that includes an array or plurality of pressure sensors and an array or plurality of heating/cooling elements or components, which may be coupled together, for preventing or reducing laminating film or material bleed out and improving thickness variation performance. The pressure sensors may provide a controller, which is coupled to the lamination tool, with real-time feedback on any thickness variations across a substrate panel and the controller may adjust the temperature output of the heating and cooling elements to locally modify the viscosity of the laminating material in one or more regions of the substrate panel to either decrease or increase the flowability of the laminating material.

公开(公告)号：US11804420B2

公开(公告)日：2023-10-31

申请号：US16020122

申请日：2018-06-27

Applicant: INTEL CORPORATION

Inventor： Brandon Marin ,  Whitney Bryks

IPC: H01L23/492 ,  H01L23/532 ,  H01L23/498 ,  H01L21/02

CPC classification number: H01L23/4922 ,  H01L23/4924 ,  H01L23/49822 ,  H01L23/49894 ,  H01L21/02112 ,  H01L23/5329

Abstract: A package substrate may include a build-up layer. The build-up layer may include a dielectric material and one or more microspheres. The one or more microspheres may include a magnetic core that includes a first material that is a first oxidation-resistant material. Further, the one or more microspheres may include a shell to encapsulate the core, and the shell may include a second material that is a second oxidation-resistant material. The package substrate may further include a metal layer coupled with the build-up layer.

公开(公告)号：US10546916B2

公开(公告)日：2020-01-28

申请号：US16024223

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Brandon C Marin ,  Praneeth Akkinepally ,  Whitney Bryks ,  Dilan Seneviratne ,  Frank Truong

IPC: H01L29/00 ,  H01L49/02 ,  H01L23/532 ,  H01L21/768 ,  H01L23/00

Abstract: Disclosed embodiments include in-recess fabricated vertical capacitor cells, that can be assembled as close to the surface of a semiconductor package substrate as the first-level interconnect surface. The in-recess fabricated vertical capacitor cells are semiconductor package-integrated capacitors. Disclosed embodiments include laminated vertical capacitor cells where a plated through-hole is twice breached to form opposing capacitor plates. The breached, plated through-hole capacitors are semiconductor package-integrated capacitors.

公开(公告)号：US20200006468A1

公开(公告)日：2020-01-02

申请号：US16024223

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Praneeth Akkinepally ,  Whitney Bryks ,  Dilan Seneviratne ,  Frank Truong

IPC: H01L49/02 ,  H01L23/532 ,  H01L21/768 ,  H01L23/00

Abstract: Disclosed embodiments include in-recess fabricated vertical capacitor cells, that can be assembled as close to the surface of a semiconductor package substrate as the first-level interconnect surface. The in-recess fabricated vertical capacitor cells are semiconductor package-integrated capacitors. Disclosed embodiments include laminated vertical capacitor cells where a plated through-hole is twice breached to form opposing capacitor plates. The breached, plated through-hole capacitors are semiconductor package-integrated capacitors.