公开(公告)号：US09874820B2

公开(公告)日：2018-01-23

申请号：US14887111

申请日：2015-10-19

申请人： Intel Deutschland GMBH

发明人： Thorsten Meyer

IPC分类号： H01L23/00 ,  G03F7/20 ,  H01L21/324 ,  H01L21/268 ,  G03F9/00 ,  H01L21/56

CPC分类号： G03F7/70433 ,  G03F7/70991 ,  G03F9/7003 ,  G03F9/7011 ,  H01L21/268 ,  H01L21/324 ,  H01L21/568 ,  H01L24/19 ,  H01L24/95 ,  H01L24/96 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A method of processing semiconductor chips includes measuring locations of semiconductor dies placed on a carrier with a scanner to generate die location information. The method includes applying a dielectric layer over the semiconductor dies and communicating the die location information to a laser assembly. The method includes aligning the laser assembly with the carrier and laser structuring the dielectric layer with the laser assembly based on the die location information generated by the scanner.

公开(公告)号：US09385105B2

公开(公告)日：2016-07-05

申请号：US14370971

申请日：2013-01-10

申请人： INTEL DEUTSCHLAND GMBH

发明人： Thorsten Meyer ,  Gerald Ofner ,  Bernd Waidhas ,  Hans-Joachim Barth ,  Sven Albers ,  Reinhard Golly ,  Philipp Riess ,  Bernd Ebersberger

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/16 ,  H01L23/538 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56

CPC分类号： H01L24/81 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/14 ,  H01L24/17 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/16 ,  H01L2224/0231 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00

摘要： A semiconductor device includes: a chip having at least one electrically conductive contact at a first side of the chip; an extension layer extending laterally from one or more sides of the chip; a redistribution layer on a surface of the extension layer and the first side, and coupled to the contact; an interposer having at least one electrically conductive contact at a first surface of the interposer and coupled to the redistribution layer, and at least one electrically conductive contact at a second surface of the interposer opposite to the first surface; a molding material at least partially enclosing the chip and the redistribution layer, and in contact with the interposer. Another semiconductor device includes: an interposer; a redistribution layer over the interposer; a circuit having first and second circuit portions, wherein the redistribution layer includes the first circuit portion, and the interposer includes the second circuit portion.

摘要翻译： 半导体器件包括：在芯片的第一侧具有至少一个导电触点的芯片; 从芯片的一个或多个侧面横向延伸的延伸层; 在所述延伸层和所述第一侧的表面上的再分布层，并且耦合到所述接触件; 插入器，在所述插入器的第一表面处具有至少一个导电接触并且耦合到所述再分配层，以及在所述插入件的与所述第一表面相对的第二表面处的至少一个导电接触; 至少部分地包围所述芯片和所述再分配层并且与所述插入件接触的模制材料。 另一半导体器件包括：插入器; 在内插器上的再分配层; 具有第一和第二电路部分的电路，其中再分配层包括第一电路部分，并且插入器包括第二电路部分。

公开(公告)号：US20160190107A1

公开(公告)日：2016-06-30

申请号：US15063579

申请日：2016-03-08

申请人： Intel Deutschland GmbH

发明人： Thorsten Meyer ,  Sven Albers ,  Andreas Wolter

IPC分类号： H01L25/10

CPC分类号： H01L25/105 ,  H01L21/568 ,  H01L22/14 ,  H01L23/31 ,  H01L23/3107 ,  H01L23/3135 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/19 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/83192 ,  H01L2224/92244 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/1461 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/16225 ,  H01L2924/00012

摘要： An electronic package includes an interposer, a die attached to a first side of the interposer, an embedded electronic package attached to a second side of the interposer, an encapsulation compound, a set of vias providing electrical paths from a first side of the electronic package to the interposer through the encapsulation compound, and a redistribution layer electrically redistributing the set of vias to form a set of interconnect-pads. Either the die or the embedded electronic package, or both, are electrically connected to the interposer.

摘要翻译： 电子封装包括插入器，附接到插入件的第一侧的管芯，附接到插入件的第二侧的嵌入式电子封装，封装化合物，从电子封装的第一侧提供电路径的一组通孔 通过所述封装化合物施加到所述插入件，以及再分布层，电再重分配所述一组通孔以形成一组互连焊盘。 芯片或嵌入式电子封装或两者都电连接到插入器。

公开(公告)号：US09985005B2

公开(公告)日：2018-05-29

申请号：US15063579

申请日：2016-03-08

申请人： Intel Deutschland GmbH

发明人： Thorsten Meyer ,  Sven Albers ,  Andreas Wolter

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/10 ,  H01L25/065 ,  H01L23/31 ,  H01L25/03 ,  H01L25/00 ,  H01L23/00 ,  H01L21/66 ,  H01L21/56

CPC分类号： H01L25/105 ,  H01L21/568 ,  H01L22/14 ,  H01L23/31 ,  H01L23/3107 ,  H01L23/3135 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/19 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/83192 ,  H01L2224/92244 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/1461 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/16225 ,  H01L2924/00012

摘要： An electronic package includes an interposer, a die attached to a first side of the interposer, an embedded electronic package attached to a second side of the interposer, an encapsulation compound, a set of vias providing electrical paths from a first side of the electronic package to the interposer through the encapsulation compound, and a redistribution layer electrically redistributing the set of vias to form a set of interconnect-pads. Either the die or the embedded electronic package, or both, are electrically connected to the interposer.

公开(公告)号：US09601475B2

公开(公告)日：2017-03-21

申请号：US15041127

申请日：2016-02-11

申请人： Intel Deutschland GmbH

发明人： Markus Brunnbauer ,  Thorsten Meyer ,  Stephan Bradl ,  Ralf Plieninger ,  Jens Pohl ,  Klaus Pressel ,  Recai Sezi

IPC分类号： H01L21/301 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L23/552 ,  H01L23/60 ,  H01L23/00 ,  H01L23/48 ,  H01L21/48

CPC分类号： H01L25/50 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/60 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1617 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2224/82 ,  H01L2924/00

摘要： A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.

公开(公告)号：US20160163682A1

公开(公告)日：2016-06-09

申请号：US15041127

申请日：2016-02-11

申请人： Intel Deutschland GmbH

发明人： Markus Brunnbauer ,  Thorsten Meyer ,  Stephan Bradl ,  Ralf Plieninger ,  Jens Pohl ,  Klaus Pressel ,  Recai Sezi

IPC分类号： H01L25/00 ,  H01L21/48 ,  H01L21/56

CPC分类号： H01L25/50 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/60 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1617 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2224/82 ,  H01L2924/00

摘要： A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.

摘要翻译： 工件具有至少两个半导体芯片，每个半导体芯片具有至少部分暴露的第一主表面和第二主表面。 所述工件还包括布置在所述至少两个半导体芯片上的导电层，所述导电层至少布置在所述第二主表面的区域上，所述模制化合物布置在所述导电层上。