公开(公告)号：US20180005961A1

公开(公告)日：2018-01-04

申请号：US15707504

申请日：2017-09-18

Applicant: International Business Machines Corporation

Inventor： Erdem Kaltalioglu ,  Andrew T. Kim ,  Chengwen Pei ,  Ping-Chuan Wang

IPC: H01L23/00 ,  H01L21/762 ,  H01L21/308 ,  H01L21/3105 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L23/562 ,  H01L21/308 ,  H01L21/31051 ,  H01L21/76283 ,  H01L29/0649 ,  H01L29/66795

Abstract: A semiconductor structure includes filled dual reinforcing trenches that reduce curvature of the semiconductor structure by stiffening the semiconductor structure. The filled dual reinforcing trenches reduce curvature by acting against transverse loading, axial loading, and/or torsional loading of the semiconductor structure that would otherwise result in semiconductor structure curvature. The filled dual reinforcing trenches may be located in an array throughout the semiconductor structure, in particular locations within the semiconductor structure, or at the perimeter of the semiconductor structure.

公开(公告)号：US09761539B2

公开(公告)日：2017-09-12

申请号：US14753768

申请日：2015-06-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ronald G. Filippi ,  Erdem Kaltalioglu ,  Andrew T. Kim ,  Ping-Chuan Wang

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L23/562 ,  H01L21/76868 ,  H01L21/76898 ,  H01L23/481

Abstract: Reinforcement structures used with a thinned wafer and methods of manufacture are provided. The method includes forming trenches or vias at least partially through a backside of a thinned wafer attached to a carrier wafer. The method further includes depositing material within the trenches or vias to form reinforcement structures on the backside of the thinned wafer. The method further includes removing excess material from a surface of the thinned wafer, which was deposited during the depositing of the material within the vias.

公开(公告)号：US09305879B2

公开(公告)日：2016-04-05

申请号：US14024694

申请日：2013-09-12

Applicant: International Business Machines Corporation

Inventor： Ronald G. Filippi ,  Erdem Kaltalioglu ,  Andrew T. Kim ,  Ping-Chuan Wang ,  Lijuan Zhang

IPC: H01L23/525 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5256 ,  H01L21/76886 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An e-fuse structure including a fuse link having a first region made of a first conductor and a second region made of a second conductor. The first conductor and the second conductor are in the same wiring level. The first conductor has a higher electrical resistance than the second conductor. The first conductor has a higher resistance to electromigration than the second conductor. The first region and the second region have a common width. The length of the first region is longer than the length of the second region.

Abstract translation: 一种电熔丝结构，包括具有由第一导体制成的第一区域和由第二导体制成的第二区域的熔丝连接。 第一导体和第二导体处于相同的布线层。 第一导体具有比第二导体更高的电阻。 第一导体比第二导体具有更高的电迁移阻力。 第一区域和第二区域具有共同的宽度。 第一区域的长度比第二区域的长度长。

公开(公告)号：US20150255417A1

公开(公告)日：2015-09-10

申请号：US14716959

申请日：2015-05-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Mukta G. Farooq ,  Erdem Kaltalioglu ,  Wei Lin ,  Spyridon Skordas ,  Kevin R. Winstel

IPC: H01L23/00 ,  H01L23/544

CPC classification number: H01L24/29 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/544 ,  H01L23/562 ,  H01L24/67 ,  H01L24/81 ,  H01L24/89 ,  H01L24/94 ,  H01L2223/5446 ,  H01L2224/13023 ,  H01L2224/13147 ,  H01L2224/13582 ,  H01L2224/13649 ,  H01L2224/13686 ,  H01L2224/81002 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81895 ,  H01L2224/94 ,  H01L2225/06593 ,  H01L2924/01025 ,  H01L2924/0537 ,  H01L2924/14 ,  H01L2924/2064 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2924/053

Abstract: A method of forming a stacked assembly of semiconductor chips can include juxtaposing and metallurgically joining kerf metal elements exposed in kerf regions of a first wafer with corresponding kerf metal elements exposed in kerf regions of a second wafer, and affixing undiced semiconductor chips of the first wafer with corresponding undiced semiconductor chips of the second wafer. The assembled wafers are then cut along the dicing lanes thereof into a plurality of individual assemblies of stacked semiconductor chips, each assembly including an undiced semiconductor chip of the first wafer and an undiced semiconductor chip of the second wafer affixed therewith.

公开(公告)号：US09082781B2

公开(公告)日：2015-07-14

申请号：US14045145

申请日：2013-10-03

Applicant: International Business Machines Corporation

Inventor： Ronald G. Filippi ,  Erdem Kaltalioglu ,  Xiao Hu Liu ,  Thomas M. shaw ,  Ping-Chuan Wang ,  Bucknell C. Webb ,  Lijuan Zhang

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L23/564 ,  H01L23/481 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor article which includes a semiconductor base portion including a semiconductor material; a back end of the line (BEOL) wiring portion on the semiconductor base portion and comprising a plurality of wiring layers having metallic wiring and insulating material, said BEOL wiring portion excluding a semiconductor material; and a guard ring in the BEOL wiring portion and surrounding a structure in the semiconductor chip, the guard ring having a zig-zag configuration.

Abstract translation: 一种半导体制品，其包括半导体材料的半导体基底部分; 在所述半导体基底部分上的所述线（BEOL）布线部分的后端，并且包括具有金属布线和绝缘材料的多个布线层，所述BEOL布线部分不包括半导体材料; 以及在BEOL布线部分中的保护环，并围绕半导体芯片中的结构，保护环具有之字形配置。

公开(公告)号：US20140332963A1

公开(公告)日：2014-11-13

申请号：US13890560

申请日：2013-05-09

Applicant: International Business Machines Corporation

Inventor： Ronald G. Filippi ,  Erdem Kaltalioglu ,  Ping-Chuan Wang ,  Lijuan Zhang

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electronic interconnect structure having a hybridized metal structure near regions of high operating temperature on an integrated circuit, and methods of making the same. The hybridized metal structure features at least two different metals in a single metallization level. The first metal is in a region of high operating temperature and the second region is in a region of normal operating temperatures. In a preferred embodiment the first metal includes aluminum and is in a first level metallization over an active area of the device while the second metal includes copper. In some embodiments, the first and second metals are not in direct physical contact. In other embodiments the first and second metals physically contact each other. In a preferred embodiment, a top surface of the first metal is not co-planar with a top surface of the second metal, despite being in the same metallization level.

Abstract translation: 一种在集成电路上具有高工作温度区域附近的杂化金属结构的电子互连结构及其制造方法。 杂化金属结构在单一金属化水平中具有至少两种不同的金属。 第一金属处于高工作温度的区域，第二区域处于正常工作温度的区域。 在优选实施例中，第一金属包括铝，并且在器件的有效区域上处于第一级金属化，而第二金属包括铜。 在一些实施例中，第一和第二金属不是直接的物理接触。 在其他实施例中，第一和第二金属物理地彼此接触。 在优选实施例中，尽管处于相同的金属化水平，第一金属的顶表面与第二金属的顶表面不共面。

公开(公告)号：US20170098616A1

公开(公告)日：2017-04-06

申请号：US14873420

申请日：2015-10-02

Applicant: International Business Machines Corporation

Inventor： Erdem Kaltalioglu ,  Andrew T. Kim ,  Chengwen Pei ,  Ping-Chuan Wang

IPC: H01L23/00 ,  H01L21/3105 ,  H01L21/762 ,  H01L21/308 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L23/562 ,  H01L21/308 ,  H01L21/31051 ,  H01L21/76283 ,  H01L29/0649 ,  H01L29/66795

Abstract: A semiconductor structure includes filled dual reinforcing trenches that reduce curvature of the semiconductor structure by stiffening the semiconductor structure. The filled dual reinforcing trenches reduce curvature by acting against transverse loading, axial loading, and/or torsional loading of the semiconductor structure that would otherwise result in semiconductor structure curvature. The filled dual reinforcing trenches may be located in an array throughout the semiconductor structure, in particular locations within the semiconductor structure, or at the perimeter of the semiconductor structure.

公开(公告)号：US09553054B2

公开(公告)日：2017-01-24

申请号：US14522083

申请日：2014-10-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Mukta G. Farooq ,  John A. Fitzsimmons ,  Erdem Kaltalioglu ,  Wei Lin ,  Spyridon Skordas ,  Kevin R. Winstel

IPC: H01L23/00 ,  H01L21/288 ,  H01L21/302 ,  H01L21/66 ,  H01L21/768 ,  H01L25/00 ,  H01L25/065 ,  H01L23/48

CPC classification number: H01L23/562 ,  H01L21/2885 ,  H01L21/302 ,  H01L21/76898 ,  H01L22/34 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Strain detection structures used with bonded wafers and chips and methods of manufacture are disclosed. The method includes forming lower metal wiring structures associated with a lower wafer structure. The method further includes bonding the lower wafer structure to an upper wafer structure and thinning the upper wafer, and forming upper metal wiring structures. The method further includes electrically linking the lower metal wiring structures to the upper metal wiring structures by formation of through silicon via structures to form an electrically connected chain extending between multiple wafer structures. The method further includes forming contacts to an outside environment which electrically contact two of the lower metal wiring structures.

Abstract translation: 公开了与键合晶片和芯片一起使用的应变检测结构和制造方法。 该方法包括形成与下晶片结构相关联的下金属布线结构。 该方法还包括将下晶片结构接合到上晶片结构并使上晶片变薄，并形成上金属布线结构。 该方法还包括通过形成穿过硅的结构将下部金属布线结构电连接到上部金属布线结构，以形成在多个晶片结构之间延伸的电连接链。 该方法还包括形成与外部环境的接触，该外部环境电接触两个下部金属布线结构。

公开(公告)号：US09059333B1

公开(公告)日：2015-06-16

申请号：US14096325

申请日：2013-12-04

Applicant: International Business Machines Corporation

Inventor： Mukta G. Farooq ,  Erdem Kaltalioglu ,  Wei Lin ,  Spyridon Skordas ,  Kevin R. Winstel

IPC: H01L21/768 ,  H01L21/78 ,  H01L23/544 ,  H01L23/00

CPC classification number: H01L24/29 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/544 ,  H01L23/562 ,  H01L24/67 ,  H01L24/81 ,  H01L24/89 ,  H01L24/94 ,  H01L2223/5446 ,  H01L2224/13023 ,  H01L2224/13147 ,  H01L2224/13582 ,  H01L2224/13649 ,  H01L2224/13686 ,  H01L2224/81002 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81895 ,  H01L2224/94 ,  H01L2225/06593 ,  H01L2924/01025 ,  H01L2924/0537 ,  H01L2924/14 ,  H01L2924/2064 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2924/053

Abstract: A method of forming a stacked assembly of semiconductor chips can include juxtaposing and metallurgically joining kerf metal elements exposed in kerf regions of a first wafer with corresponding kerf metal elements exposed in kerf regions of a second wafer, and affixing undiced semiconductor chips of the first wafer with corresponding undiced semiconductor chips of the second wafer. The assembled wafers are then cut along the dicing lanes thereof into a plurality of individual assemblies of stacked semiconductor chips, each assembly including an undiced semiconductor chip of the first wafer and an undiced semiconductor chip of the second wafer affixed therewith.

Abstract translation: 一种形成半导体芯片的层叠组件的方法可以包括将暴露在第一晶片的切口区域中的切口金属元件与暴露在第二晶片的切口区域中的相应的切口金属元件并列并且冶金连接的方法，并且固定第一晶片的未切割的半导体芯片 与第二晶片的相应未切割的半导体芯片。 然后将组装好的晶片沿切割通道切割成堆叠的半导体芯片的多个独立组件，每个组件包括第一晶片的未切割的半导体芯片和与其固定的第二晶片的未切割的半导体芯片。

公开(公告)号：US09059166B2

公开(公告)日：2015-06-16

申请号：US13890560

申请日：2013-05-09

Applicant: International Business Machines Corporation

Inventor： Ronald G. Filippi ,  Erdem Kaltalioglu ,  Ping-Chuan Wang ,  Lijuan Zhang

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electronic interconnect structure having a hybridized metal structure near regions of high operating temperature on an integrated circuit, and methods of making the same. The hybridized metal structure features at least two different metals in a single metallization level. The first metal is in a region of high operating temperature and the second region is in a region of normal operating temperatures. In a preferred embodiment the first metal includes aluminum and is in a first level metallization over an active area of the device while the second metal includes copper. In some embodiments, the first and second metals are not in direct physical contact. In other embodiments the first and second metals physically contact each other. In a preferred embodiment, a top surface of the first metal is not co-planar with a top surface of the second metal, despite being in the same metallization level.

Abstract translation: 一种在集成电路上具有高工作温度区域附近的杂化金属结构的电子互连结构及其制造方法。 杂化金属结构在单一金属化水平中具有至少两种不同的金属。 第一金属处于高工作温度的区域，第二区域处于正常操作温度的区域。 在优选实施例中，第一金属包括铝，并且在器件的有效区域上处于第一级金属化，而第二金属包括铜。 在一些实施例中，第一和第二金属不是直接的物理接触。 在其他实施例中，第一和第二金属物理地彼此接触。 在优选实施例中，尽管处于相同的金属化水平，第一金属的顶表面与第二金属的顶表面不共面。