Patent search ap:("INTERNATIONAL BUSINESS MACHINES CORPORATION") AND inv:"John A. Fitzsimmons" Page 1

1.

发明授权
Self-aligned contact structure 有权
Title translation: 自对准接触结构

公开(公告)号：US09548244B2

公开(公告)日：2017-01-17

申请号：US14837854

申请日：2015-08-27

Applicant: International Business Machines Corporation

Inventor： Rosa A. Orozco-Teran , Ravikumar Ramachandran , John A. Fitzsimmons , Russell H Arndt , David L. Rath

IPC: H01L21/768 , H01L29/49 , H01L29/45 , H01L21/28 , H01L23/522 , H01L23/528 , H01L23/532 , H01L29/417 , H01L29/78

CPC classification number: H01L21/76897 , H01L21/28079 , H01L21/76805 , H01L21/76814 , H01L21/76816 , H01L21/76831 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L23/53238 , H01L23/53266 , H01L23/53295 , H01L29/41775 , H01L29/42372 , H01L29/45 , H01L29/4958 , H01L29/78 , H01L2924/0002 , H01L2924/00

Abstract: Embodiments of present invention provide a method of forming a semiconductor structure. The method includes forming a semiconductor structure having a first metal layer and a plurality of dielectric layers on top of the first metal layer; creating one or more openings through the plurality of dielectric layers to expose the first metal layer underneath the plurality of dielectric layers; causing the one or more openings to expand downward into the first metal layer and expand horizontally into areas underneath the plurality of dielectric layers; applying a layer of lining material in lining sidewalls of the one or more openings inside the plurality of dielectric layers; and filling the expanded one or more openings with a conductive material.

Abstract translation: 本发明的实施例提供一种形成半导体结构的方法。该方法包括在第一金属层的顶部上形成具有第一金属层和多个电介质层的半导体结构; 通过所述多个电介质层产生一个或多个开口以暴露所述多个电介质层下面的所述第一金属层; 使所述一个或多个开口向下扩展到所述第一金属层中并且水平地扩展到所述多个介电层下面的区域中; 在所述多个电介质层内的所述一个或多个开口的衬里侧壁中施加一层衬里材料; 并用导电材料填充膨胀的一个或多个开口。

2.

发明申请
WAFER TO WAFER ALIGNMENT 有权
Title translation: WAFER TO WAFER对准

公开(公告)号：US20160178344A1

公开(公告)日：2016-06-23

申请号：US14576072

申请日：2014-12-18

Applicant: International Business Machines Corporation

Inventor： Mukta G. Farooq , John A. Fitzsimmons , Spyridon Skordas

IPC: G01B7/30

CPC classification number: G01B7/31 , H01L22/34 , H01L23/544 , H01L2223/5442 , H01L2223/54426 , H01L2223/5446

Abstract: Wafer to wafer alignment which includes a first semiconductor wafer and a second semiconductor wafer. The first and second semiconductor wafers have selectively-activated alignment arrays for aligning the first semiconductor wafer with the second semiconductor wafer. Each of the alignment arrays include an alignment structure which includes an antenna connected to a semiconductor device. The antenna in each of the alignment arrays is selectively activated to act as a charge source or as a charge sensing receptor. The alignment arrays are located in the kerf areas of the semiconductor wafers. The semiconductor wafers are aligned when the charge sources on one semiconductor wafer match with the charge sensing receptors on the other semiconductor wafer.

Abstract translation: 晶片对准包括第一半导体晶片和第二半导体晶片。第一和第二半导体晶片具有用于使第一半导体晶片与第二半导体晶片对准的选择性激活对准阵列。每个对准阵列包括对准结构，其包括连接到半导体器件的天线。每个对准阵列中的天线被选择性地激活以用作电荷源或电荷感测接收器。对准阵列位于半导体晶片的切口区域中。当一个半导体晶片上的电荷源与另一个半导体晶片上的电荷感测接收体匹配时，半导体晶片对准。

3.

发明申请
ACIDIFIED CONDUCTIVE WATER FOR DEVELOPER RESIDUE REMOVAL 审中-公开
Title translation: 用于开发者残留去除的酸化导电水

公开(公告)号：US20160041471A1

公开(公告)日：2016-02-11

申请号：US14453882

申请日：2014-08-07

Applicant: International Business Machines Corporation

Inventor： Guillaume D. Briend , Vishal Chhabra , John A. Fitzsimmons

IPC: G03F7/40

CPC classification number: G03F7/405

Abstract: The present invention relates generally to semiconductor fabrication lithography and, more particularly, to a method and composition for reducing post-development defects and residues that may remain on a photoresist after development of the photoresist without causing substantial damage to the photoresist. The method may include rinsing the photoresist and the semiconductor device with ozonated acidified conductive water composed of a combination of ozone and a gaseous acid dissolved in deionized water.

Abstract translation: 本发明一般涉及半导体制造光刻术，更具体地说，涉及一种减少显影后缺陷的残留物和残余物的方法和组合物，其可以在光致抗蚀剂显影之后保留在光致抗蚀剂上而不会对光致抗蚀剂造成实质的损害。该方法可以包括用由臭氧和溶解在去离子水中的气态的组合组成的臭氧化的酸化导电水冲洗光致抗蚀剂和半导体器件。

4.

发明申请
SELF-ALIGNED CONTACT STRUCTURE 有权

公开(公告)号：US20150200137A1

公开(公告)日：2015-07-16

申请号：US14157125

申请日：2014-01-16

Applicant: International Business Machines Corporation

Inventor： Rosa A. Orozco-Teran , Ravikumar Ramachandran , John A. Fitzsimmons , Russell H. Arndt , David L. Rath

IPC: H01L21/768 , H01L29/45 , H01L21/28 , H01L29/49

CPC classification number: H01L21/76897 , H01L21/28079 , H01L21/76805 , H01L21/76814 , H01L21/76816 , H01L21/76831 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L23/53238 , H01L23/53266 , H01L23/53295 , H01L29/41775 , H01L29/42372 , H01L29/45 , H01L29/4958 , H01L29/78 , H01L2924/0002 , H01L2924/00

Abstract: Embodiments of present invention provide a method of forming a semiconductor structure. The method includes forming a semiconductor structure having a first metal layer and a plurality of dielectric layers on top of the first metal layer; creating one or more openings through the plurality of dielectric layers to expose the first metal layer underneath the plurality of dielectric layers; causing the one or more openings to expand downward into the first metal layer and expand horizontally into areas underneath the plurality of dielectric layers; applying a layer of lining material in lining sidewalls of the one or more openings inside the plurality of dielectric layers; and filling the expanded one or more openings with a conductive material.

5.

发明授权
Selective etch chemistry for gate electrode materials 有权
Title translation: 栅电极材料的选择性蚀刻化学

公开(公告)号：US09070625B2

公开(公告)日：2015-06-30

申请号：US13828650

申请日：2013-03-14

Applicant: International Business Machines Corporation

Inventor： John A. Fitzsimmons , David L. Rath , Muthumanickam Sankarapandian

IPC: H01L21/283 , H01L21/8238 , H01L21/3213 , C23F1/02 , C23F1/32 , C23G1/20

CPC classification number: C23F1/40 , C09K13/00 , C23F1/02 , C23F1/32 , C23G1/205 , H01L21/283 , H01L21/32134 , H01L21/823842

Abstract: A chemical solution including an aqueous solution, an oxidizing agent, and a pH stabilizer selected from quaternary ammonium salts and quaternary ammonium alkali can be employed to remove metallic materials in cavities for forming a semiconductor device. For example, metallic materials in gate cavities for forming a replacement gate structure can be removed by the chemical solution of the present disclosure with, or without, selectivity among multiple metallic materials such as work function materials. The chemical solution of the present disclosure provides different selectivity among metallic materials than known etchants in the art.

Abstract translation: 可以使用包含水溶液，氧化剂和选自季铵盐和季铵碱的pH稳定剂的化学溶液来除去用于形成半导体器件的空腔中的金属材料。例如，用于形成替代栅极结构的栅极腔中的金属材料可以通过本发明的化学溶液被去除，或者在多种金属材料如功函数材料中具有或不具有选择性。本公开的化学溶液在金属材料中提供与本领域中已知的蚀刻剂不同的选择性。

6.

发明授权
Sidewalls of electroplated copper interconnects 有权
Title translation: 电镀铜互连的侧壁

公开(公告)号：US09040407B2

公开(公告)日：2015-05-26

申请号：US14043079

申请日：2013-10-01

Applicant: International Business Machines Corporation

Inventor： Mukta G. Farooq , John A. Fitzsimmons , Troy L. Graves-Abe

IPC: H05K3/42 , H01L23/48 , H01L23/532 , H01L21/768

CPC classification number: H05K3/423 , H01L21/76844 , H01L21/76846 , H01L21/76858 , H01L21/76898 , H01L23/481 , H01L23/53209 , H01L23/53214 , H01L23/53238 , H01L23/53242 , H01L23/53257 , H01L2924/0002 , Y10T428/12764 , H01L2924/00

Abstract: A method including depositing an alloying layer along a sidewall of an opening and in direct contact with a seed layer, the alloying layer includes a crystalline structure that cannot serve as a seed for plating a conductive material, exposing the opening to an electroplating solution including the conductive material, the conductive material is not present in the alloying layer, applying an electrical potential to a cathode causing the conductive material to deposit from the electroplating solution onto the cathode exposed at the bottom of the opening and causing the opening to fill with the conductive material, the cathode includes an exposed portion of the seed layer and excludes the alloying layer, and forming a first intermetallic compound along an intersection between the alloying layer and the conductive material, the first intermetallic compound is formed as a precipitate within a solid solution of the alloying layer and the conductive material.

Abstract translation: 一种方法，包括沿着开口的侧壁沉积合金层并与种子层直接接触，所述合金化层包括不能用作电镀导电材料的种子的晶体结构，将开口暴露于包括导电材料不存在于合金化层中，向阴极施加电势，导致导电材料从电镀溶液沉积到露出在开口底部的阴极上并使开口填充导电材料材料中，阴极包括种子层的暴露部分，不包括合金层，沿着合金层和导电材料之间的交点形成第一金属间化合物，第一金属间化合物形成为沉淀在固溶体合金层和导电材料。

7.

发明申请
BOTTOM-UP PLATING OF THROUGH-SUBSTRATE VIAS 有权
Title translation: 底层六角形底层镀层

公开(公告)号：US20150056804A1

公开(公告)日：2015-02-26

申请号：US14522633

申请日：2014-10-24

Applicant: International Business Machines Corporation

Inventor： Mukta G. Farooq , John A. Fitzsimmons , Troy L. Graves-Abe

IPC: H01L21/768 , H01L21/683 , H01L23/00

CPC classification number: H01L21/76898 , H01L21/6835 , H01L21/6836 , H01L21/76879 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2221/68359 , H01L2224/03462 , H01L2224/03622 , H01L2224/0401 , H01L2224/05556 , H01L2224/05572 , H01L2224/05611 , H01L2224/05639 , H01L2224/05647 , H01L2224/05655 , H01L2224/05671 , H01L2224/11 , H01L2224/13025 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/94 , Y10T29/41 , H01L2924/00012 , H01L2924/00014 , H01L2224/03 , H01L2924/014

Abstract: According to one embodiment of the present invention, a method of plating a TSV hole in a substrate is provided. The TSV hole may include an open end terminating at a conductive pad, a stack of wiring levels, and a plurality of chip interconnects. The method of plating a TSV may include attaching a handler to the plurality of chip interconnects, the handler having a conductive layer in electrical contact with the plurality of chip interconnects; exposing a closed end of the TSV hole, including the conductive pad, to an electrolyte solution; and applying an electrical potential along an electrical path from the conductive layer to the conductive pad causing conductive material from the electrolyte solution to deposit on the conductive pad and within the TSV hole, the electrical path including the conductive layer, the plurality of chip interconnects, the stack of wiring levels and the conductive pad.

Abstract translation: 根据本发明的一个实施例，提供了一种在衬底中电镀TSV孔的方法。 TSV孔可以包括终止于导电焊盘的开口端，布线层的堆叠以及多个芯片互连。电镀TSV的方法可以包括将处理器附接到多个芯片互连件，处理器具有与多个芯片互连电接触的导电层; 将包括导电垫的TSV孔的封闭端暴露于电解质溶液中; 以及沿着从所述导电层到所述导电焊盘的电路径施加电势，从而导致来自所述电解质溶液的导电材料沉积在所述导电焊盘和所述TSV孔内，所述电路包括所述导电层，所述多个芯片互连，布线层叠和导电垫。

8.

发明申请
CLEANING COMPOSITION AND PROCESS FOR CLEANING SEMICONDUCTOR DEVICES AND/OR TOOLING DURING MANUFACTURING THEREOF 审中-公开
Title translation: 清洁组合物和清洁半导体器件和/或其制造过程中的清洁

公开(公告)号：US20150024989A1

公开(公告)日：2015-01-22

申请号：US14510381

申请日：2014-10-09

Applicant: International Business Machines Corporation

Inventor： Vishal Chhabra , Laertis Economikos , John A. Fitzsimmons , James Hannah , Mahmoud Khojasteh , Jennifer Muncy

IPC: H01L21/02 , C11D7/08 , C11D7/26

CPC classification number: H01L21/02057 , C11D3/042 , C11D3/2079 , C11D3/2086 , C11D7/08 , C11D7/265 , C11D7/267 , C11D11/0047

Abstract: Cleaning solutions and processes for cleaning semiconductor devices or semiconductor tooling during manufacture thereof generally include contacting the semiconductor devices or semiconductor tooling with an acidic aqueous cleaning solution free of a fluorine containing compound, the acidic aqueous cleaning solution including at least one antioxidant and at least one non-oxidizing acid.

Abstract translation: 用于在制造过程中清洁半导体器件或半导体工具的清洁溶液和工艺通常包括使半导体器件或半导体工具与不含氟化合物的酸性含水清洁溶液接触，所述酸性含水清洁溶液包含至少一种抗氧化剂和至少一种抗氧化剂非氧化性酸。

9.

发明申请
SIDEWALLS OF ELECTROPLATED COPPER INTERCONNECTS 有权

公开(公告)号：US20140027296A1

公开(公告)日：2014-01-30

申请号：US14043079

申请日：2013-10-01

Applicant: International Business Machines Corporation

Inventor： Mukta G. Farooq , John A. Fitzsimmons , Troy L. Graves-Abe

IPC: H05K3/42

CPC classification number: H05K3/423 , H01L21/76844 , H01L21/76846 , H01L21/76858 , H01L21/76898 , H01L23/481 , H01L23/53209 , H01L23/53214 , H01L23/53238 , H01L23/53242 , H01L23/53257 , H01L2924/0002 , Y10T428/12764 , H01L2924/00

Abstract: A structure formed in an opening having a substantially vertical sidewall defined by a non-metallic material and having a substantially horizontal bottom defined by a conductive pad, the structure including a diffusion barrier covering the sidewall and a fill composed of conductive material. The structure including a first intermetallic compound separating the diffusion barrier from the conductive material, the first intermetallic compound comprises an alloying material and the conductive material, and is mechanically bound to the conductive material, the alloying material is at least one of the materials selected from the group of chromium, tin, nickel, magnesium, cobalt, aluminum, manganese, titanium, zirconium, indium, palladium, and silver; and a first high friction interface located between the diffusion barrier and the first intermetallic compound and parallel to the sidewall of the opening, wherein the first high friction interface results in a mechanical bond between the diffusion barrier and the first intermetallic compound.