公开(公告)号：US10276500B2

公开(公告)日：2019-04-30

申请号：US15806441

申请日：2017-11-08

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Wei Lin ,  Takeshi Nogami

IPC分类号： H01L21/76 ,  H01L21/4763 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

摘要： A semiconductor structure including a first metal line and a second metal line in a dielectric layer, the first metal line and the second metal line are adjacent and within the same dielectric level; an air gap structure in the dielectric layer and between the first metal line and the second metal line, wherein the air gap structure includes an air gap oxide layer and an air gap; and a barrier layer between the air gap structure and the first metal line, wherein the barrier layer is an oxidized metal layer.

公开(公告)号：US10056272B2

公开(公告)日：2018-08-21

申请号：US15811738

申请日：2017-11-14

申请人： International Business Machines Corporation

发明人： Wei Lin ,  Spyridon Skordas ,  Robert R. Young, Jr.

IPC分类号： H01L21/76 ,  H01L21/67 ,  B23K20/02 ,  H01L23/00

CPC分类号： H01L21/67092 ,  B23K20/02 ,  H01L24/75 ,  H01L24/83 ,  H01L2224/8301 ,  H01L2924/37001

摘要： A wafer bonding method includes placing a top wafer on a top bonding framework including a plurality of outlet holes around a periphery of the top bonding framework. A bottom wafer is placed on a bottom bonding framework that includes a plurality of inlet holes around a periphery of the bottom bonding framework. The top bonding framework is in overlapping relation to the bottom bonding framework such that a gap exist between the top wafer and the bottom wafer. A gas stream is circulated through the gap between the top wafer and the bottom wafer entering the gap through one or more of the plurality of inlet holes and exiting the gap through one or more of the plurality of outlet holes. The gas stream replaces any existing ambient moisture from the gap between the top wafer and the bottom wafer.

公开(公告)号：US10047264B2

公开(公告)日：2018-08-14

申请号：US14546394

申请日：2014-11-18

申请人： International Business Machines Corporation

发明人： Wei Lin

IPC分类号： C09K5/14 ,  C08G18/42 ,  C08G18/32 ,  C08G18/20 ,  C08G18/76 ,  C08G18/66 ,  C09J175/06 ,  C08G18/00

摘要： The present invention relates generally to thermally conductive adhesives for thermal interfaces in electronic packaging, and more particularly, to a polymer-based composite thermal interface material (“TIM”) with an inter-penetrating network (IPN) polymer matrix consisting of polyurethane and an epoxy that is fully crosslinked. The IPN polymer matrix is designed to improve overall thermal conductivity by the altering the dispersion/distribution of thermally conductive fillers, the filler/polymer interfaces, and/or phonon scattering behaviors in the composite.

公开(公告)号：US09922851B2

公开(公告)日：2018-03-20

申请号：US14269457

申请日：2014-05-05

申请人： International Business Machines Corporation

发明人： Wei Lin ,  Spyridon Skordas ,  Robert R. Young, Jr.

IPC分类号： H01L21/30 ,  H01L21/67 ,  H01L23/00 ,  B23K20/02

CPC分类号： H01L21/67092 ,  B23K20/02 ,  H01L24/75 ,  H01L24/83 ,  H01L2224/8301 ,  H01L2924/37001

摘要： A wafer bonding method includes placing a top wafer on a top bonding framework including a plurality of outlet holes around a periphery of the top bonding framework. A bottom wafer is placed on a bottom bonding framework that includes a plurality of inlet holes around a periphery of the bottom bonding framework. The top bonding framework is in overlapping relation to the bottom bonding framework such that a gap exist between the top wafer and the bottom wafer. A gas stream is circulated through the gap between the top wafer and the bottom wafer entering the gap through one or more of the plurality of inlet holes and exiting the gap through one or more of the plurality of outlet holes. The gas stream replaces any existing ambient moisture from the gap between the top wafer and the bottom wafer.

公开(公告)号：US20180068953A1

公开(公告)日：2018-03-08

申请号：US15806441

申请日：2017-11-08

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Wei Lin ,  Takeshi Nogami

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522

CPC分类号： H01L23/53209 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76867 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/00 ,  H01L2924/0002

摘要： A semiconductor structure including a first metal line and a second metal line in a dielectric layer, the first metal line and the second metal line are adjacent and within the same dielectric level; an air gap structure in the dielectric layer and between the first metal line and the second metal line, wherein the air gap structure includes an air gap oxide layer and an air gap; and a barrier layer between the air gap structure and the first metal line, wherein the barrier layer is an oxidized metal layer.

公开(公告)号：US09847295B2

公开(公告)日：2017-12-19

申请号：US14831897

申请日：2015-08-21

申请人： International Business Machines Corporation

发明人： Wei Lin ,  Takeshi Nogami

IPC分类号： H01L21/76 ,  H01L21/4763 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L23/53209 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76867 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/00 ,  H01L2924/0002

摘要： A semiconductor structure including a first metal line and a second metal line in a dielectric layer, the first metal line and the second metal line are adjacent and within the same dielectric level; an air gap structure in the dielectric layer and between the first metal line and the second metal line, wherein the air gap structure includes an air gap oxide layer and an air gap; and a barrier layer between the air gap structure and the first metal line, wherein the barrier layer is an oxidized metal layer.

公开(公告)号：US20170221850A1

公开(公告)日：2017-08-03

申请号：US15491329

申请日：2017-04-19

申请人： International Business Machines Corporation

发明人： Wei Lin ,  Leathen Shi ,  Spyridon Skordas ,  Kevin R. Winstel

IPC分类号： H01L23/00

CPC分类号： H01L24/32 ,  H01L21/187 ,  H01L21/76251 ,  H01L21/76254 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/27 ,  H01L24/29 ,  H01L24/80 ,  H01L24/83 ,  H01L24/94 ,  H01L33/0079 ,  H01L2224/03452 ,  H01L2224/03845 ,  H01L2224/04 ,  H01L2224/04026 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05187 ,  H01L2224/0519 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/08145 ,  H01L2224/27452 ,  H01L2224/27616 ,  H01L2224/29023 ,  H01L2224/29083 ,  H01L2224/29187 ,  H01L2224/32145 ,  H01L2224/80896 ,  H01L2224/80907 ,  H01L2224/80948 ,  H01L2224/81896 ,  H01L2224/83 ,  H01L2224/838 ,  H01L2224/83896 ,  H01L2224/83907 ,  H01L2224/83948 ,  H01L2224/94 ,  H01L2924/05442 ,  H01L2924/06 ,  H01L2924/0715 ,  H01L2924/3512 ,  H01L2924/35121 ,  Y02P80/30 ,  H01L2224/80 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A wafer-to-wafer semiconductor device includes a first wafer substrate having a first bonding layer formed on a first bulk substrate layer. A second wafer substrate includes a second bonding layer formed on a second bulk substrate layer. The second bonding layer is bonded to the first bonding layer to define a bonding interface. At least one of the first wafer substrate and the second wafer substrate includes a crack-arresting film layer configured to increase a bonding energy of the bonding interface.

公开(公告)号：US20150348842A1

公开(公告)日：2015-12-03

申请号：US14823428

申请日：2015-08-11

申请人： International Business Machines Corporation

发明人： Wei Lin ,  Spyridon Skordas ,  Tuan A. Vo

IPC分类号： H01L21/768 ,  H01L21/308 ,  H01L25/065 ,  H01L23/522 ,  H01L21/02 ,  H01L25/00 ,  H01L23/48 ,  H01L21/311

CPC分类号： H01L21/76898 ,  H01L21/02175 ,  H01L21/02244 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/02282 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76829 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5222 ,  H01L23/5226 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06541 ,  H01L2924/0002 ,  Y10T428/24331 ,  H01L2924/00

摘要： A manganese oxide layer is deposited as a hard mask layer on substrate including at least a dielectric material layer. An optional silicon oxide layer may be formed over the manganese oxide layer. A patterned photoresist layer can be employed to etch the optional silicon oxide layer and the manganese oxide layer. An anisotropic etch process is employed to etch the dielectric material layer within the substrate. The dielectric material layer can include silicon oxide and/or silicon nitride, and the manganese oxide layer can be employed as an effective etch mask that minimizes hard mask erosion and widening of the etched trench. The manganese oxide layer may be employed as an etch mask for a substrate bonding process.

摘要翻译： 在包括至少介电材料层的基板上沉积氧化锰层作为硬掩模层。 可以在氧化锰层上形成任选的氧化硅层。 可以使用图案化的光致抗蚀剂层来蚀刻可选的氧化硅层和氧化锰层。 采用各向异性蚀刻工艺来蚀刻衬底内的介电材料层。 介电材料层可以包括氧化硅和/或氮化硅，并且锰氧化物层可以用作有效蚀刻掩模，其最小化蚀刻沟槽的硬掩模腐蚀和加宽。 锰氧化物层可以用作衬底粘合工艺的蚀刻掩模。

公开(公告)号：US09190303B2

公开(公告)日：2015-11-17

申请号：US14716236

申请日：2015-05-19

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Douglas C. La Tulipe, Jr. ,  Wei Lin ,  Spyridon Skordas ,  Kevin R. Winstel

IPC分类号： G01R31/26 ,  G06F19/00 ,  H01L21/67 ,  H01L23/00 ,  H01L21/324

CPC分类号： H01L21/67259 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/324 ,  H01L22/12 ,  H01L22/20 ,  H01L24/83 ,  H01L24/94

摘要： A bonding layer of a first wafer article is thermally treated and a bonding layer of a second wafer article is thermally treated in accordance with first and second process parameters, respectively prior to bonding the first wafer article with the second wafer article. First and second grid distortion in the first and second wafer articles is measured and a difference is determined between the first and second grid distortions. A prediction is made for maintaining the difference within a prescribed tolerance. At least one of the first process parameters and the second process parameters is conditionally varied in accordance with the prediction. The thermal treating of the first and second wafer articles can then be performed with respect to another pair of the first and second wafer articles prior to bonding to one another through their respective bonding layers.

摘要翻译： 对第一晶片制品的接合层进行热处理，并且在将第一晶片制品与第二晶片制品接合之前，分别根据第一和第二工艺参数对第二晶片制品的粘结层进行热处理。 测量第一和第二晶片制品中的第一和第二网格变形，并且在第一和第二格栅失真之间确定差异。 进行预测以将差异保持在规定的公差内。 第一处理参数和第二处理参数中的至少一个根据预测有条件地变化。 然后可以在通过其各自的结合层彼此粘合之前相对于另一对第一和第二晶片制品执行第一和第二晶片制品的热处理。

公开(公告)号：US20150221610A1

公开(公告)日：2015-08-06

申请号：US14685973

申请日：2015-04-14

申请人： International Business Machines Corporation

发明人： Wei Lin ,  Spyridon Skordas ,  Tuan A. Vo

IPC分类号： H01L23/00 ,  B32B38/18

CPC分类号： H01L24/98 ,  B32B38/0012 ,  B32B38/1825 ,  B32B2457/14 ,  H01L21/02035 ,  H01L21/2007 ,  H01L21/304 ,  H01L21/67092 ,  H01L21/67288 ,  H01L22/12 ,  H01L22/20 ,  H01L24/80 ,  Y10T156/1168 ,  Y10T156/17

摘要： Separating bonded wafers. A bonded wafer pair is mounted between first and second bonding chucks having flat chuck faces, the first bonding chuck face including adjustable zones capable of movement relative to each other, at least a component of the relative movement is along an axis that is perpendicular to the flat first bonding chuck face. The adjustable zones of the first face are moved relative to each other in a coordinated manner such that a widening gap is formed between the bonding faces of the wafer pair.

摘要翻译： 分离粘结晶片 粘合晶片对安装在具有平坦卡盘面的第一和第二接合卡盘之间，第一接合卡盘面包括能够相对于彼此运动的可调节区域，相对运动的至少一部分沿着垂直于 平面第一粘接卡盘面。 第一面的可调节区域以协调的方式相对于彼此移动，使得在晶片对的接合面之间形成加宽的间隙。