Concurrently Forming nFET and pFET Gate Dielectric Layers
    3.
    发明申请
    Concurrently Forming nFET and pFET Gate Dielectric Layers 有权
    并联形成nFET和pFET栅介质层

    公开(公告)号:US20140187028A1

    公开(公告)日:2014-07-03

    申请号:US13732455

    申请日:2013-01-02

    CPC classification number: H01L21/823857

    Abstract: Embodiments include methods of forming an nFET-tuned gate dielectric and a pFET-tuned gate dielectric. Methods may include forming a high-k layer above a substrate having a pFET region and an nFET region, forming a first sacrificial layer, a pFET work-function metal layer, and a second sacrificial layer above the first high-k layer in the pFET region, and an nFET work-function metal layer above the first high-k layer in the nFET region and above the second sacrificial layer in the pFET region. The first high-k layer then may be annealed to form an nFET gate dielectric layer in the nFET region and a pFET gate dielectric layer in the pFET region. The first high-k layer may be annealed in the presence of a nitrogen source to cause atoms from the nitrogen source to diffuse into the first high-k layer in the nFET region.

    Abstract translation: 实施例包括形成nFET调谐的栅极电介质和pFET调谐的栅极电介质的方法。 方法可以包括在pFET区域和nFET区域上形成高k层,形成第一牺牲层,pFET功函数金属层和在pFET中的第一高k层上方的第二牺牲层 区域,以及在nFET区域中的第一高k层上方的nFET功函数金属层,并且在pFET区域中的第二牺牲层上方。 第一高k层然后可以退火以在nFET区域中形成nFET栅极介电层,并在pFET区域中形成pFET栅极电介质层。 第一高k层可以在存在氮源的情况下进行退火,以使来自氮源的原子扩散到nFET区域中的第一高k层。

    DEPOSITION OF PURE METALS IN 3D STRUCTURES
    4.
    发明申请
    DEPOSITION OF PURE METALS IN 3D STRUCTURES 审中-公开
    沉积在三维结构中的纯金属

    公开(公告)号:US20140183051A1

    公开(公告)日:2014-07-03

    申请号:US13732642

    申请日:2013-01-02

    CPC classification number: C25D3/54 C25D5/00 C25D5/003 C25D17/001 C25D17/002

    Abstract: A system and method generate atomic hydrogen (H) for deposition of a pure metal in a three-dimensional (3D) structure. The method includes forming a monolayer of a compound that includes the pure metal. The method also includes depositing the monolayer on the 3D structure and immersing the 3D structure with the monolayer in an electrochemical cell chamber including an electrolyte. Applying a negative bias voltage to the 3D structure with the monolayer and a positive bias voltage to a counter electrode generates atomic hydrogen from the electrolyte and deposits the pure metal from the monolayer in the 3D structure.

    Abstract translation: 一种系统和方法产生用于在三维(3D)结构中沉积纯金属的原子氢(H)。 该方法包括形成包含纯金属的化合物的单层。 该方法还包括在3D结构上沉积单层并将具有单层的3D结构浸入包括电解质的电化学电池室中。 使用单层将三角形结构施加负偏置电压并对正电极施加正偏置电压,从电解液中产生原子氢,并在3D结构中从单层沉积纯金属。

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