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    Method of manufacturing semiconductor devices including replacement metal gate process incorporating a conductive dummy gate layer
    5.
    发明授权
    Method of manufacturing semiconductor devices including replacement metal gate process incorporating a conductive dummy gate layer 有权
    包括具有导电虚拟栅极层的替代金属栅极工艺的半导体器件的制造方法

    公开(公告)号：US08835292B2

    公开(公告)日：2014-09-16

    申请号：US13664744

    申请日：2012-10-31

    Applicant: International Business Machines Corporation ,  Globalfoundries Inc.

    Inventor： Michael P. Chudzik ,  Min Dai ,  Xiang Hu ,  Jinping Liu ,  Yanxiang Liu ,  Xiaodong Yang

    IPC: H01L21/3205

    CPC classification number: H01L29/66545 ,  H01L21/2807 ,  H01L21/28088 ,  H01L21/823437 ,  H01L21/823462

    Abstract: A method of manufacturing a semiconductor device including a replacement metal gate process incorporating a conductive dummy gate layer (e.g., silicon germanium (SiGe), titanium nitride, etc.) and a related are disclosed. The method includes forming an oxide layer on a substrate; removing a gate portion of the oxide layer from the substrate in a first region of the semiconductor device; forming a conductive dummy gate layer on the semiconductor device in the first region; and forming a gate on the semiconductor device, the gate including a gate conductor disposed in the first region and directly connected to the substrate.

    Abstract translation: 公开了一种制造半导体器件的方法，该半导体器件包括结合导电虚拟栅极层（例如硅锗（SiGe），氮化钛等）的替代金属栅极工艺）和相关的方法。 该方法包括在衬底上形成氧化物层; 在所述半导体器件的第一区域中从所述衬底去除所述氧化物层的栅极部分; 在所述第一区域中的所述半导体器件上形成导电虚拟栅极层; 以及在所述半导体器件上形成栅极，所述栅极包括设置在所述第一区域中并直接连接到所述衬底的栅极导体。

    Fabrication of higher-k dielectrics
    6.
    发明授权
    Fabrication of higher-k dielectrics 有权
    高k电介质的制备

    公开(公告)号：US09478425B1

    公开(公告)日：2016-10-25

    申请号：US15045474

    申请日：2016-02-17

    Applicant: International Business Machines Corporation

    Inventor： Michael P. Chudzik ,  Min Dai ,  Dominic J. Schepis ,  Shahab Siddiqui

    IPC: H01L21/8238 ,  H01L21/283 ,  H01L21/324

    CPC classification number: H01L21/823857 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28202 ,  H01L27/092 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

    Abstract: A method of manufacturing a semiconductor structure, and the resultant structure. The method includes forming an oxide layer above a substrate. The method includes forming a metal layer above the oxide layer. The method includes forming a first capping layer above the metal layer. A material forming the first capping layer may be titanium oxide, or titanium oxynitride. The method includes annealing the semiconductor structure. Annealing the semiconductor structure may result in diffusing a metal from the metal layer into the oxide layer.

    Abstract translation: 一种制造半导体结构的方法，以及所得结构。 该方法包括在衬底上形成氧化物层。 该方法包括在氧化物层上形成金属层。 该方法包括在金属层上方形成第一覆盖层。 形成第一覆盖层的材料可以是氧化钛或氮氧化钛。 该方法包括退火半导体结构。 退火半导体结构可能导致金属从金属层扩散到氧化物层中。

    FIELD EFFECT TRANSISTORS HAVING MULTIPLE EFFECTIVE WORK FUNCTIONS
    8.
    发明申请
    FIELD EFFECT TRANSISTORS HAVING MULTIPLE EFFECTIVE WORK FUNCTIONS 有权
    具有多种有效工作功能的场效应晶体管

    公开(公告)号：US20160005831A1

    公开(公告)日：2016-01-07

    申请号：US14320831

    申请日：2014-07-01

    Applicant: International Business Machines Corporation

    Inventor： Takashi Ando ,  Min Dai ,  Balaji Kannan ,  Siddarth A. Krishnan ,  Unoh Kwon

    IPC: H01L29/49 ,  H01L21/8234 ,  H01L27/088

    CPC classification number: H01L21/823412 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/785

    Abstract: Selective deposition of a silicon-germanium surface layer on semiconductor surfaces can be employed to provide two types of channel regions for field effect transistors. Anneal of an adjustment oxide material on a stack of a silicon-based gate dielectric and a high dielectric constant (high-k) gate dielectric can be employed to form an interfacial adjustment oxide layer contacting a subset of channel regions. Oxygen deficiency can be induced in portions of the high-k dielectric layer overlying the interfacial adjustment oxide layer by deposition of a first work function metallic material layer and a capping layer and a subsequent anneal. Oxygen deficiency can be selectively removed by physically exposing portions of the high-k dielectric layer. A second work function metallic material layer and a gate conductor layer can be deposited and planarized to form gate electrodes that provide multiple effective work functions.

    Abstract translation: 硅 - 锗表面层在半导体表面上的选择性沉积可用于为场效应晶体管提供两种类型的沟道区。 在硅基栅极电介质和高介电常数（高k）栅极电介质的堆叠上的调整氧化物材料的退火可以用于形成接触通道区域子集的界面调整氧化物层。 通过沉积第一功函数金属材料层和封盖层和随后的退火，可以在覆盖界面调整氧化物层的高k电介质层的部分中诱导氧缺乏。 可以通过物理暴露高k电介质层的部分来选择性地去除氧缺乏。 可以将第二功函数金属材料层和栅极导体层沉积并平坦化以形成提供多个有效功函数的栅电极。

    Concurrently Forming nFET and pFET Gate Dielectric Layers
    9.
    发明申请
    Concurrently Forming nFET and pFET Gate Dielectric Layers 有权
    并联形成nFET和pFET栅介质层

    公开(公告)号：US20140187028A1

    公开(公告)日：2014-07-03

    申请号：US13732455

    申请日：2013-01-02

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

    Inventor： Takashi Ando ,  Maryjane Brodsky ,  Michael P. Chudzik ,  Min Dai ,  Siddarth A. Krishnan ,  Joseph F. Shepard, JR. ,  Yanfeng Wang ,  Jinping Liu

    IPC: H01L21/8238

    CPC classification number: H01L21/823857

    Abstract: Embodiments include methods of forming an nFET-tuned gate dielectric and a pFET-tuned gate dielectric. Methods may include forming a high-k layer above a substrate having a pFET region and an nFET region, forming a first sacrificial layer, a pFET work-function metal layer, and a second sacrificial layer above the first high-k layer in the pFET region, and an nFET work-function metal layer above the first high-k layer in the nFET region and above the second sacrificial layer in the pFET region. The first high-k layer then may be annealed to form an nFET gate dielectric layer in the nFET region and a pFET gate dielectric layer in the pFET region. The first high-k layer may be annealed in the presence of a nitrogen source to cause atoms from the nitrogen source to diffuse into the first high-k layer in the nFET region.

    Abstract translation: 实施例包括形成nFET调谐的栅极电介质和pFET调谐的栅极电介质的方法。 方法可以包括在pFET区域和nFET区域上形成高k层，形成第一牺牲层，pFET功函数金属层和在pFET中的第一高k层上方的第二牺牲层 区域，以及在nFET区域中的第一高k层上方的nFET功函数金属层，并且在pFET区域中的第二牺牲层上方。 第一高k层然后可以退火以在nFET区域中形成nFET栅极介电层，并在pFET区域中形成pFET栅极电介质层。 第一高k层可以在存在氮源的情况下进行退火，以使来自氮源的原子扩散到nFET区域中的第一高k层。

    DEPOSITION OF PURE METALS IN 3D STRUCTURES
    10.
    发明申请
    DEPOSITION OF PURE METALS IN 3D STRUCTURES 审中-公开
    沉积在三维结构中的纯金属

    公开(公告)号：US20140183051A1

    公开(公告)日：2014-07-03

    申请号：US13732642

    申请日：2013-01-02

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Michael P. Chudzik ,  Min Dai ,  Rishikesh Krishnan ,  Joseph F. Shepard, JR.

    IPC: C25D3/54

    CPC classification number: C25D3/54 ,  C25D5/00 ,  C25D5/003 ,  C25D17/001 ,  C25D17/002

    Abstract: A system and method generate atomic hydrogen (H) for deposition of a pure metal in a three-dimensional (3D) structure. The method includes forming a monolayer of a compound that includes the pure metal. The method also includes depositing the monolayer on the 3D structure and immersing the 3D structure with the monolayer in an electrochemical cell chamber including an electrolyte. Applying a negative bias voltage to the 3D structure with the monolayer and a positive bias voltage to a counter electrode generates atomic hydrogen from the electrolyte and deposits the pure metal from the monolayer in the 3D structure.

    Abstract translation: 一种系统和方法产生用于在三维（3D）结构中沉积纯金属的原子氢（H）。 该方法包括形成包含纯金属的化合物的单层。 该方法还包括在3D结构上沉积单层并将具有单层的3D结构浸入包括电解质的电化学电池室中。 使用单层将三角形结构施加负偏置电压并对正电极施加正偏置电压，从电解液中产生原子氢，并在3D结构中从单层沉积纯金属。

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