公开(公告)号：US4417159A

公开(公告)日：1983-11-22

申请号：US293830

申请日：1981-08-18

申请人： Jack A. Dorler ,  Joseph M. Mosley ,  Richard O. Seeger ,  Stephen D. Weitzel

发明人： Jack A. Dorler ,  Joseph M. Mosley ,  Richard O. Seeger ,  Stephen D. Weitzel

IPC分类号： H03F1/00 ,  H03K5/02 ,  H03K17/04 ,  H03K17/06 ,  H03K17/12 ,  H03K17/66 ,  H03K19/013 ,  H03K19/018 ,  H03K5/00

CPC分类号： H03K19/013 ,  H03K19/01806 ,  H03K5/02

摘要： A driver circuit for a capacitively loaded line employs the charge storage capacitance of a diode for raising the base of a driver transistor above the circuit power supply voltage level so as to pull up the line to within a transistor base-emitter voltage drop of the power supply voltage level. The driver is easily fabricated in integrated circuit form, as no capacitors, either on or off chip, are required.The driver circuit includes a driver transistor, the collector of which is connected to the power supply and the emitter of which is connected to the line. A switching transistor has an input voltage applied between its base and emitter. A diode is connected between the switching and driver transistors, the anode being connected to the base of the driver transistor, and the cathode being connected to the collector of the switching transistor.In response to a first input signal, the switching transistor turns on, forward biasing the diode and building up a voltage thereon as a result of the diode's charge storage capacitance. In response to a second input signal, the switching transistor turns off, raising the anode to the power supply voltage, and raising the cathode (and the base of the driver transistor connected thereto) to a voltage higher than the power supply voltage. The emitter of the driver transistor (and the line connected thereto) is thus pulled up to a value nominally approaching the power supply voltage, despite the base-emitter voltage drop of the driver transistor.

摘要翻译： 用于电容负载线路的驱动器电路采用用于将驱动晶体管的基极升高到电路电源电压电平以上的二极管的电荷存储电容，以便将线上拉到功率的晶体管基极 - 发射极电压降内 电源电压电平。 驱动器易于以集成电路形式制造，因为不需要电源或芯片上的电容器。 驱动器电路包括驱动晶体管，其集电极连接到电源，其发射极连接到线路。 开关晶体管具有施加在其基极和发射极之间的输入电压。 二极管连接在开关晶体管和驱动晶体管之间，阳极连接到驱动晶体管的基极，阴极连接到开关晶体管的集电极。 响应于第一输入信号，开关晶体管导通，由于二极管的电荷存储电容，正向偏置二极管并在其上建立电压。 响应于第二输入信号，开关晶体管截止，将阳极升高到电源电压，并将阴极（以及连接到其的驱动晶体管的基极）升高到高于电​​源电压的电压。 因此，尽管驱动晶体管的基极 - 发射极电压降，驱动晶体管（及其连接的线）的发射极被上拉到标称接近电源电压的值。

公开(公告)号：US4346343A

公开(公告)日：1982-08-24

申请号：US150762

申请日：1980-05-16

申请人： Erich Berndlmaier ,  Jack A. Dorler ,  Joseph M. Mosley ,  Stephen D. Weitzel

发明人： Erich Berndlmaier ,  Jack A. Dorler ,  Joseph M. Mosley ,  Stephen D. Weitzel

IPC分类号： H03K19/00 ,  G05F1/46 ,  G06F1/04 ,  G06F1/10 ,  H03K3/03 ,  H03K5/00 ,  H03K19/0175 ,  H03K19/086 ,  H03L7/089 ,  H03L7/099

CPC分类号： H03L7/0805 ,  G05F1/466 ,  H03K3/0315 ,  H03K3/0322 ,  H03L7/0995 ,  H03L7/089

摘要： An on chip delay regulator circuit which varies the power in logic or array circuits on the chip so as to minimize, or eliminate, chip to chip circuit speed differences caused by power supply variations and/or lot to lot process differences, temperature, etc.The on chip delay regulator accomplishes this by comparing a reference signal to an on chip generated signal which is sensitive to power supply changes, lot to lot process changes, temperature, etc. The comparison creates an error signal which is used to change the power (current or voltage) supplied to the on chip circuits. By changing the circuit power, the circuit speed (gate delay) is increased or decreased as necessary to maintain a relatively constant circuit speed on each chip.For example, a plurality of integrated circuit chips each contain an on chip delay regulator. The on chip delay regulator on each chip of said plurality of integrated circuit chips receives and responds to the same signal (or clock). Each chip provides a discrete on chip generated signal related to the parameters of the chip. The gate delay (or speed) of the circuitry on each chip is determined by its on chip delay regulator under control of the common reference signal (or clock).

摘要翻译： 一种片上延迟调节器电路，其改变芯片上的逻辑或阵列电路中的功率，以便最小化或消除由电源变化和/或批处理差异，温度等引起的芯片对芯片电路速度差异。 片上延迟调节器通过将参考信号与对电源变化敏感的片上产生信号进行比较来实现，这些信号对于批次处理变化，温度等是很敏感的。比较产生用于改变功率的误差信号（ 电流或电压）提供给片上电路。 通过改变电路功率，根据需要增加或减小电路速度（门延迟），以在每个芯片上保持相对恒定的电路速度。 例如，多个集成电路芯片各自包含片上延迟调节器。 所述多个集成电路芯片的每个芯片上的片上延迟调节器接收并响应相同的信号（或时钟）。 每个芯片提供与芯片参数相关的离散片上产生的信号。 每个芯片上的电路的门延迟（或速度）由其片上延迟调节器在公共参考信号（或时钟）的控制下确定。

公开(公告)号：US4535531A

公开(公告)日：1985-08-20

申请号：US360730

申请日：1982-03-22

申请人： Harsaran S. Bhatia ,  Jack A. Dorler ,  Santosh P. Gaur ,  John S. Lechaton ,  Joseph M. Mosley ,  Gurumakonda R. Srinivasan

发明人： Harsaran S. Bhatia ,  Jack A. Dorler ,  Santosh P. Gaur ,  John S. Lechaton ,  Joseph M. Mosley ,  Gurumakonda R. Srinivasan

IPC分类号： H01L29/73 ,  H01L21/3065 ,  H01L21/331 ,  H01L21/822 ,  H01L21/8222 ,  H01L27/04 ,  H01L27/082 ,  H01L29/10 ,  H01L21/82

CPC分类号： H01L27/0825 ,  H01L21/3065 ,  H01L21/8222 ,  H01L29/1004

摘要： A process is described which permits the fabrication of very narrow base width bipolar transistors in selected areas of an integrated circuit chip and bipolar transistors of wider base width on other selected areas of the same integrated circuit chip. The ability to selectively vary the transistor characteristics from one region of an integrated circuit chip to another provides a degree of freedom for design of integrated circuits which is valuable. The bipolar transistors on an integrated circuit chip are processed up to the point of emitter formation using conventional techniques. But, prior to the emitter formation, the base area which is to be the emitters of the selected region having the very narrow base transistors is dry etched using reactive ion etching. The existing silicon nitride/silicon dioxide layers with the emitter opening therein are used as the etching mask for this reactive ion etching procedure. Once the etching is completed to the desired depth, the normal processing is resumed to form the emitter and rest of the metallization.

摘要翻译： 描述了一种方法，其允许在集成电路芯片的选定区域中制造非常窄的基极宽度双极晶体管，并且在同一集成电路芯片的其它选定区域上制造宽基极宽度的双极晶体管。 将晶体管特性从集成电路芯片的一个区域选择性地变化到另一个区域的能力提供了有价值的集成电路设计的自由度。 使用常规技术将集成电路芯片上的双极晶体管加工成发射点形成点。 但是，在发射极形成之前，将使用反应离子蚀刻干法蚀刻作为具有非常窄的基极晶体管的选定区域的发射极的基极区域。 将其中具有发射极开口的现有氮化硅/二氧化硅层用作该反应离子蚀刻程序的蚀刻掩模。 一旦蚀刻完成到期望的深度，则恢复正常处理以形成发射器和金属化的其余部分。

公开(公告)号：US4409498A

公开(公告)日：1983-10-11

申请号：US221684

申请日：1980-12-30

申请人： Jack A. Dorler ,  Joseph M. Mosley

发明人： Jack A. Dorler ,  Joseph M. Mosley

IPC分类号： H03K19/018 ,  H03K17/04 ,  H03K17/60 ,  H03K19/013 ,  H03K19/086 ,  H03K17/16 ,  H03K19/092

CPC分类号： H03K19/086 ,  H03K19/0136

摘要： A current controlled gate performing a NOR function utilizes a pair of transistors acting as current mirrors that receive a DC bias through a large resistor. This bias occurs when an input transistor is positive to insure that one of the current mirror transistors will saturate when the input transistors are "off" and the other will be driven into saturation when either of the input transistors is "on". When all inputs are negative, one of the current mirror transistors saturates thereby reducing the current to the input transistors effectively to zero. The saturation results in the collector-base capacitance increasing very rapidly such that the input assumes the characteristics of a common emitter due to the large capacitance existing in the collector of the current mirror transistor. An active push-pull output is produced with a single collector path from input to output.

摘要翻译： 执行NOR功能的电流控制栅极利用一对晶体管，其作为通过大电阻器接收DC偏置的电流镜。 当输入晶体管为正时，发生偏压，以确保当输入晶体管“截止”时电流镜晶体管中的一个将饱和，而当任一个输入晶体管“导通”时，另一个将被驱动为饱和。 当所有输入为负时，电流镜晶体管之一饱和，从而将输入晶体管的电流有效地降低到零。 饱和度导致集电极 - 基极电容非常快速地增加，使得由于存在于电流镜晶体管的集电极中的大电容，输入采用公共发射极的特性。 通过从输入到输出的单个收集器路径产生有源推挽输出。

公开(公告)号：US4508981A

公开(公告)日：1985-04-02

申请号：US392982

申请日：1982-06-28

申请人： Jack A. Dorler ,  Joseph M. Mosley ,  Stephen D. Weitzel

发明人： Jack A. Dorler ,  Joseph M. Mosley ,  Stephen D. Weitzel

IPC分类号： H01L21/822 ,  H01L21/8222 ,  H01L27/04 ,  H01L27/06 ,  H03K17/16 ,  H03K3/013 ,  H03K19/003

CPC分类号： H03K17/16

摘要： Compensation circuit means for inclusion in an off-chip driver circuit is provided to reduce self-induced switching noise in a multi-chip module semiconductor structure. A module section interconnects the chips and the chips have a power supply and power leads respectively. The compensation circuit means, which is coupled across the output transistor circuit of the off-chip driver, may comprise one or more serially connected diodes. The diode (or diodes) may be formed by the base collector junction of a bipolar transistor.

摘要翻译： 提供了用于包含在片外驱动电路中的补偿电路，以减少多芯片模块半导体结构中的自感应开关噪声。 模块部分互连芯片，芯片分别具有电源和电源引线。 耦合在片外驱动器的输出晶体管电路两端的补偿电路装置可以包括一个或多个串联连接的二极管。 二极管（或二极管）可以由双极晶体管的基极集电极结形成。

公开(公告)号：US4383216A

公开(公告)日：1983-05-10

申请号：US229417

申请日：1981-01-29

申请人： Jack A. Dorler ,  Michael O. Jenkins ,  Joseph M. Mosley ,  Stephen D. Weitzel

发明人： Jack A. Dorler ,  Michael O. Jenkins ,  Joseph M. Mosley ,  Stephen D. Weitzel

IPC分类号： H01L21/822 ,  G05F1/46 ,  G06F1/08 ,  H01L27/00 ,  H01L27/04 ,  H03K5/00 ,  H03K19/00 ,  H03K19/0175

CPC分类号： G05F1/466

摘要： An on chip delay regulator circuit which varies the power in logic or array circuits on the chip so as to minimize, or eliminate, chip to chip circuit speed differences caused by power supply variations and/or lot to lot process differences, temperature, etc. The on chip delay regulator accomplishes this by comparing a periodic reference signal to a periodic on chip generated signal which is sensitive to power supply changes, lot to lot process changes, temperature, etc. The comparison creates an error signal which is used to change the power (current or voltage) supplied to the on chip circuits. By changing the circuit power, the circuit speed (gate delay) is increased or decreased as necessary to maintain a relatively constant circuit speed on each chip. For example, a plurality of integrated circuit chips each contain an on chip delay regulator. The on chip delay regulator on each chip of said plurality of integrated circuit chips receives and responds to the same signal (or clock). Each chip provides a discrete on chip generated signal related to the parameters of the chip. The gate delay (or speed) of the circuitry on each chip is determined by its on chip delay regulator under control of the common reference signal (or clock). At least certain of the chips include an AC measurement circuit for comparing the periodicity of said reference signal with the periodicity of said on generated chip signal and cooperating with the delay regulator thereof to provide one of three discrete electrical manifestations.

摘要翻译： 一种片上延迟调节器电路，其改变芯片上的逻辑或阵列电路中的功率，以便最小化或消除由电源变化和/或批处理差异，温度等引起的芯片对芯片电路速度差异。 片上延迟调节器通过将周期性参考信号与对电源变化，批次处理变化，温度等敏感的周期性片上产生信号进行比较来实现。比较创建一个误差信号，用于改变 提供给片上电路的功率（电流或电压）。 通过改变电路功率，根据需要增加或减小电路速度（门延迟），以在每个芯片上保持相对恒定的电路速度。 例如，多个集成电路芯片各自包含片上延迟调节器。 所述多个集成电路芯片的每个芯片上的片上延迟调节器接收并响应相同的信号（或时钟）。 每个芯片提供与芯片参数相关的离散片上产生的信号。 每个芯片上的电路的门延迟（或速度）由其片上延迟调节器在公共参考信号（或时钟）的控制下确定。 至少某些芯片包括AC测量电路，用于将所述参考信号的周期性与所述上述生成的芯片信号的周期进行比较，并与其延迟调节器协作以提供三种离散电气表现之一。

公开(公告)号：US5254891A

公开(公告)日：1993-10-19

申请号：US870654

申请日：1992-04-20

申请人： Jack A. Dorler ,  Francesco M. Masci

发明人： Jack A. Dorler ,  Francesco M. Masci

IPC分类号： H03K19/003 ,  H03K17/60 ,  H03K19/02

CPC分类号： H03K19/00323 ,  H03K19/00369

摘要： CMOSFETs control the power in a bipolar logic gate to regulate its operating speed and hence its delay. In a specific embodiment of the invention, an n-channel CMOSFET controls the constant current through an emitter-coupled current switch, comprised of a pair of bipolar integrated circuit transistors. A p-channel CMOSFET, in series with each collector of the switch pair, establishes the collector voltage so as to maintain constant the output swing of the gate as the power through the gate is varied in order to regulate the gate delay. An error signal, indicative of factors that can cause variations in gate delay and the inverse of the error signal are generated by an on-chip circuit. The error signal is coupled to the n-channel CMOSFET and the inverse of the error signal is coupled to the p-channel CMOSFET. Thus, as the switch current is decreased in order to increase the gate delay, the collector impedance is simultaneously increased so the collector voltage, and hence the gate swing, remains constant. Similarly, when the switch current is increased, the collector impedance is decreased.

摘要翻译： CMOSFET控制双极逻辑门中的功率来调节其工作速度，从而调节其延迟。 在本发明的具体实施例中，n沟道CMOSFET通过由一对双极集成电路晶体管组成的发射极耦合电流开关来控制恒定电流。 与开关对的每个集电极串联的p沟道CMOSFET建立集电极电压，以便通过栅极的功率变化来保持栅极的输出摆幅恒定，以便调节栅极延迟。 指示可能导致门延迟变化的因素和误差信号的反相的误差信号由片上电路产生。 误差信号耦合到n沟道CMOSFET，并且误差信号的反相耦合到p沟道CMOSFET。 因此，随着开关电流减小以增加栅极延迟，集电极阻抗同时增加，因此集电极电压，因此栅极摆动保持恒定。 类似地，当开关电流增加时，集电极阻抗减小。

公开(公告)号：US4746817A

公开(公告)日：1988-05-24

申请号：US26229

申请日：1987-03-16

申请人： Dennis C. Banker ,  Allan H. Dansky ,  Jack A. Dorler ,  Walter S. Klara ,  Frank M. Masci ,  Steven J. Zier ,  Adrian Zuckerman

发明人： Dennis C. Banker ,  Allan H. Dansky ,  Jack A. Dorler ,  Walter S. Klara ,  Frank M. Masci ,  Steven J. Zier ,  Adrian Zuckerman

IPC分类号： H03K19/01 ,  H03K17/04 ,  H03K17/567 ,  H03K19/00 ,  H03K19/08 ,  H03K19/0944

CPC分类号： H03K19/001 ,  H03K19/09448

摘要： A BIFET logic circuit for quickly switching an output line from a high level to a reference level. The BICMOS circuit comprises a push-pull circuit including a first bipolar transistor for driving current into an output line, and a second bipolar transistor for sinking current from the output line; a CFET logic circuit for performing a logic function and including at least one N type FET for providing current to the base of the second bipolar transistor when a set of input lines to the CFET circuit has a first set of predetermined values; and a resistive means for connecting one of the source or drain of the at least one NFET to a power supply to provide a source of base current to the second bipolar transistor, even when the output line drops in voltage. This circuit is especially advantageous for driving low threshold CFET circuits. In a preferred embodiment, the circuit further includes a device for preventing a voltage differential of more than a predetermined amount between the base and emitter of the first bipolar transistor, to thereby ensure proper push-pull operation of the bipolar transistors.

公开(公告)号：US5258661A

公开(公告)日：1993-11-02

申请号：US870653

申请日：1992-04-20

申请人： Dennis C. Banker ,  Jack A. Dorler ,  Walter S. Klara ,  Francesco M. Masci

发明人： Dennis C. Banker ,  Jack A. Dorler ,  Walter S. Klara ,  Francesco M. Masci

IPC分类号： H03K19/003 ,  H03K19/086 ,  H03K3/29 ,  H03K5/153

CPC分类号： H03K19/086 ,  H03K19/00353

摘要： This invention contemplates the provision of a noise immune integrated circuit receiver in which the voltage reference to one side of an emitter-coupled current switch moves in response to the input signal, in a direction opposite the input signal. This provides the gate with a threshold hysteresis, making it immune to noise without requiring a large swing in input signal.

摘要翻译： 本发明考虑提供一种噪声免疫集成电路接收器，其中发射极耦合电流开关的一侧的电压基准响应于输入信号在与输入信号相反的方向上移动。 这为门提供了门限滞后，使其免受噪声的影响，而不需要输入信号的大幅摆幅。

公开(公告)号：US4709166A

公开(公告)日：1987-11-24

申请号：US865700

申请日：1986-05-22

申请人： Dennis C. Banker ,  Jack A. Dorler ,  John N. Hryckowian

发明人： Dennis C. Banker ,  Jack A. Dorler ,  John N. Hryckowian

IPC分类号： G06F11/16 ,  H03K19/003 ,  H03K19/082 ,  G06F7/34 ,  H03K19/088

CPC分类号： H03K19/00392 ,  G06F11/1608 ,  H03K19/082

摘要： Disclosed is a Complementary Cascoded Logic (C.sup.2 L) Circuit which performs the AND-INVERT (AI) (or NAND) function. The AND function is implemented with input PNP transistors and the invert function is implemented with a first NPN transistor. An inverted NPN transistor serves as a current source for the first NPN. A first low voltage Schottky diode is serially connected between the emitter of the first NPN transistor and the emitter of the inverted NPN current source transistor. The first Schottky diode precludes, under certain conditions, simultaneous conduction of the first NPN transistor and the inverted transistor. Oppositely poled second and third low voltage Schottky diodes are utilized via an emitter follower output to provide an output voltage swing of V.sub.R .+-.V.sub.F, where V.sub.R is a reference voltage and V.sub.F is the potential drop across a Schottky diode. The low power high speed logic circuit (C.sup.2 L) has particular utility in redundant circuit applications.

摘要翻译： 公开了一种执行AND-INVERT（AI）（或NAND）功能的互补Cascoded Logic（C2L）电路。 AND功能由输入PNP晶体管实现，反相功能由第一NPN晶体管实现。 反向NPN晶体管用作第一NPN的电流源。 第一低电压肖特基二极管串联连接在第一NPN晶体管的发射极和反相NPN电流源晶体管的发射极之间。 第一肖特基二极管阻止了在某些条件下第一NPN晶体管和反相晶体管的同时导通。 通过射极跟随器输出使用相对极化的第二和第三低电压肖特基二极管，以提供VR +/- VF的输出电压摆幅，其中VR是参考电压，VF是肖特基二极管上的电位降。 低功率高速逻辑电路（C2L）在冗余电路应用中具有特殊的用途。