公开(公告)号：US4804626A

公开(公告)日：1989-02-14

申请号：US921508

申请日：1986-10-22

申请人： Dominique Bellet ,  Jack R. Wands ,  Mehmet Ozturk

发明人： Dominique Bellet ,  Jack R. Wands ,  Mehmet Ozturk

IPC分类号： G01N33/53 ,  C07K7/06 ,  C07K7/08 ,  C07K14/00 ,  C07K14/575 ,  C07K16/00 ,  C07K16/26 ,  C07K17/08 ,  C07K17/10 ,  C12N5/10 ,  C12P21/08 ,  C12R1/91 ,  G01N33/577

CPC分类号： C07K16/26 ,  C07K2317/34 ,  Y10S435/81 ,  Y10S436/80 ,  Y10S436/804 ,  Y10S436/808 ,  Y10S436/813 ,  Y10S436/814 ,  Y10S436/818 ,  Y10S436/819 ,  Y10S530/808 ,  Y10S530/809

摘要： A highly sensitive and specific monoclonal-immuno-radiometric assay (M-IRMA) for hCG, using monoclonal antibodies (Mabs) directed against a 37-amino acid synthetic polypeptide analogous to the carboxyl terminus (CTP) of beta-hCG. Accordingly, in one embodiment, a method is described for the determination of human chorionic gonadotrThe present invention was made utilizing funds of the United States Government. The U.S. government is therefore granted a royalty-free, non-exclusive, world wide, paid-up license in this invention.

摘要翻译： 使用针对类似于β-hCG的羧基末端（CTP）的37-氨基酸合成多肽的单克隆抗体（Mabs），用于hCG的高度灵敏和特异性的单克隆免疫辐射测定（M-IRMA）。 因此，在一个实施方案中，描述了用于测定样品中人绒毛膜促性腺激素的方法，其包括：（a）使所述样品与结合于载体的第一捕获单克隆抗体和第二捕获单克隆抗体接触，其中 所述第一和第二捕获抗体对人绒毛膜促性腺激素的β-亚基的羧基末端区域的不同表位具有表征特异性; （b）将步骤（a）的组分在足以在所述人绒毛膜促性腺激素，所述第一捕获单克隆抗体，所述第二捕获单克隆抗体和所述载体之间形成免疫复合物的条件下孵育一段时间; （c）向步骤（b）的所述载体添加可检测标记的指示剂单克隆抗体，其中所述指示剂单克隆抗体对人绒毛膜促性腺激素的α-亚单位具有表皮特异性; （d）确定所述载体中或液相中可检测标记的指示剂单克隆抗体。

公开(公告)号：US4933275A

公开(公告)日：1990-06-12

申请号：US791114

申请日：1985-10-24

申请人： Jack R. Wands ,  Mehmet Ozturk ,  Dominique Bellet

发明人： Jack R. Wands ,  Mehmet Ozturk ,  Dominique Bellet

IPC分类号： C07K14/195 ,  C07K14/005 ,  C07K14/575 ,  C07K16/00 ,  C07K16/26 ,  C07K19/00 ,  C12N5/00 ,  C12N5/10 ,  C12N15/00 ,  C12N15/02 ,  C12P21/00 ,  C12P21/08 ,  C12R1/91 ,  G01N33/53 ,  G01N33/577

CPC分类号： C07K16/26 ,  Y10S435/81 ,  Y10S435/975 ,  Y10S436/814 ,  Y10S436/817 ,  Y10S436/818

摘要： A method for the determination of a free protein subunit of a quaternary protein in a sample, which comprises:(a) contacting a sample with a first immunological binding partner which is or will be bound to a carrier, wherein the first immunological binding partner binds epitopic determinants bindable only on the free protein subunit;(b) incubating the components of step (a) for a period of time and under conditions sufficient to form an immune complex between the free protein subunit, the first immunological binding partner, and the carrier;(c) separating the carrier of step (b) from the sample;(d) adding to the carrier of step (c), a detectably-labeled second immunological binding partner, wherein the second immunological binding partner binds epitopic determinants bindable on both the free protein subunit and the quaternary protein; and(e) determining the detectably-labeled second immunological binding partner in the carrier or in liquid phase.

摘要翻译： 一种用于测定样品中季蛋白质的游离蛋白质亚基的方法，其包括：（a）使样品与第一免疫结合配偶体接触，所述第一免疫结合配偶体与载体结合或将结合到载体上，其中所述第一免疫结合配偶体结合 仅在游离蛋白亚基上结合的表位决定簇; （b）将步骤（a）的组分在足以在游离蛋白质亚基，第一免疫结合配偶体和载体之间形成免疫复合物的条件下孵育一段时间; （c）将步骤（b）的载体与样品分离; （d）向步骤（c）的载体添加可检测标记的第二免疫结合配偶体，其中所述第二免疫结合配偶体结合可结合游离蛋白质亚基和季蛋白的表位决定簇; 和（e）确定载体中或液相中的可检测标记的第二免疫结合配偶体。

公开(公告)号：US06071705A

公开(公告)日：2000-06-06

申请号：US469629

申请日：1995-06-06

申请人： Jack R. Wands ,  Jerome Gross ,  Mehmet Ozturk ,  Suzanne de la Monte

发明人： Jack R. Wands ,  Jerome Gross ,  Mehmet Ozturk ,  Suzanne de la Monte

IPC分类号： G01N33/53 ,  A61K39/395 ,  A61K51/00 ,  C07H21/04 ,  C07K1/22 ,  C07K14/435 ,  C07K14/47 ,  C07K16/00 ,  C07K16/18 ,  C12N5/10 ,  C12N15/09 ,  C12P21/00 ,  C12Q1/68 ,  G01N33/577 ,  G01N33/68

CPC分类号： C12Q1/6883 ,  C07K14/474 ,  C07K16/18 ,  G01N33/6878 ,  G01N33/6896 ,  C12Q2600/158 ,  G01N2800/2821 ,  Y10S436/804 ,  Y10S436/811

摘要： This invention relates to a method of detecting and diagnosing neurological disease or dysfunction using antibodies against a neurological form of Pancreatic Thread Protein (nPTP). Specifically, this invention is directed to a method of diagnosing Alzheimer's Disease, Down's Syndrome, and other neurological diseases or dysfunctions by using monoclonal antibodies, combination of those monoclonal antibodies or nucleic acid probes, to detect nPTP. The invention also relates to a recombinant DNA molecule encoding PTP and to the substantially pure form of nPTP. The invention additionally relates to a method of diagnosing pancreatic disease using antibodies against Pancreatic Thread Protein.

摘要翻译： 本发明涉及使用针对胰腺线蛋白（nPTP）神经病学形式的抗体检测和诊断神经疾病或功能障碍的方法。 具体地，本发明涉及通过使用单克隆抗体，那些单克隆抗体或核酸探针的组合来检测nPTP来诊断阿尔茨海默病，唐氏综合征和其他神经疾病或功能障碍的方法。 本发明还涉及编码PTP的重组DNA分子和基本上纯的形式的nPTP。 本发明还涉及使用针对胰线螺蛋白的抗体诊断胰腺疾病的方法。

公开(公告)号：US5250452A

公开(公告)日：1993-10-05

申请号：US717631

申请日：1991-06-19

申请人： Mehmet Ozturk ,  Jimmie Wortman

发明人： Mehmet Ozturk ,  Jimmie Wortman

IPC分类号： H01L21/28 ,  H01L29/49 ,  H01L21/441

CPC分类号： H01L29/4925 ,  H01L21/2807 ,  Y10S148/059 ,  Y10S148/105

摘要： The invention is a method of depositing a layer of polycrystalline silicon on a silicon dioxide substrate until the layer of polycrystalline silicon is thick enough to support the deposition of germanium thereon, but while thin enough to substantially avoid the deleterious effects on the characteristics of semiconductor device structure that the deposition of polycrystalline silicon would otherwise potentially cause. The polycrystalline layer is then exposed to a germanium containing gas at a temperature below the temperature at which germanium will deposit on silicon dioxide alone while preventing native growth of silicon dioxide on the polycrystalline silicon layer, and for a time sufficient for a desired thickness of polycrystalline germanium to be deposited on the layer of polycrystalline silicon.

摘要翻译： 本发明是一种在二氧化硅衬底上沉积多晶硅层的方法，直到多晶硅层足够厚以支持其上的锗沉积，但是同时足够薄以基本上避免对半导体器件的特性的有害影响 多晶硅的沉积否则可能导致的结构。 然后将多晶层暴露于含锗气体的温度，该温度低于锗将单独沉积在二氧化硅上的温度，同时防止二氧化硅在多晶硅层上的天然生长，并且足以达到期望厚度的多晶 锗沉积在多晶硅层上。

公开(公告)号：US20070029553A1

公开(公告)日：2007-02-08

申请号：US11199313

申请日：2005-08-08

申请人： Mehmet Ozturk ,  Veena Misra ,  Saurabh Chopra

发明人： Mehmet Ozturk ,  Veena Misra ,  Saurabh Chopra

IPC分类号： H01L21/00 ,  H01L31/00 ,  H01L29/768 ,  H01L29/00 ,  H01L27/148

CPC分类号： H01L29/78639 ,  H01L29/66628 ,  H01L29/66757 ,  H01L29/7848 ,  H01L29/78687

摘要： A method of fabricating a semiconductor device includes forming a strained first semiconductor layer on an insulating layer that is between second semiconductor layers. The strained first semiconductor layer may be epitaxially grown from the second semiconductor layers to extend onto the insulating layer between the second semiconductor layers. The second semiconductor layers have a lattice constant that is different than that of the first semiconductor layer, such that strain may be created in the first semiconductor layer. Related devices are also discussed.

公开(公告)号：US20050156180A1

公开(公告)日：2005-07-21

申请号：US11065085

申请日：2005-02-24

申请人： Zhibo Zhang ,  Veena Misra ,  Salah Bedair ,  Mehmet Ozturk

发明人： Zhibo Zhang ,  Veena Misra ,  Salah Bedair ,  Mehmet Ozturk

IPC分类号： H01L21/20 ,  H01L29/06 ,  H01L29/12 ,  H01L27/15 ,  H01L31/0328 ,  H01L33/00

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/02395 ,  H01L21/02463 ,  H01L21/02488 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/02642 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/125 ,  H01L29/127 ,  Y10S977/762

摘要： Methods of forming a nano-scale electronic and optoelectronic devices include forming a substrate having a semiconductor layer therein and a substrate insulating layer on the semiconductor layer. An etching template having a first array of non-photolithographically defined nano-channels extending therethrough, is formed on the substrate insulating layer. This etching template may comprise an anodized metal oxide, such as an anodized aluminum oxide (AAO) thin film. The substrate insulating layer is then selectively etched to define a second array of nano-channels therein. This selective etching step preferably uses the etching template as an etching mask to transfer the first array of nano-channels to the underlying substrate insulating layer, which may be thinner than the etching template. An array of semiconductor nano-pillars is then formed in the second array of nano-channels. The semiconductor nano-pillars in the array may have an average diameter in a range between about 8 nm and about 50 nm. The semiconductor nano-pillars are also preferably homoepitaxial or heteroepitaxial with the semiconductor layer.

摘要翻译： 形成纳米级电子和光电子器件的方法包括在其中形成其中具有半导体层的衬底和在半导体层上的衬底绝缘层。 在衬底绝缘层上形成具有非光刻限定的纳米通道的第一阵列的蚀刻模板。 该蚀刻模板可以包括阳极氧化的金属氧化物，例如阳极氧化的氧化铝（AAO）薄膜。 然后选择性地蚀刻衬底绝缘层以在其中限定纳米通道的第二阵列。 该选择蚀刻步骤优选使用蚀刻模板作为蚀刻掩模，将第一纳米通道阵列转移到下面的衬底绝缘层，其可以比蚀刻模板更薄。 然后在第二纳米通道阵列中形成半导体纳米柱阵列。 阵列中的半导体纳米柱可以具有在约8nm和约50nm之间的范围内的平均直径。 半导体纳米柱也优选与半导体层同质外延或异质外延。

公开(公告)号：US5101247A

公开(公告)日：1992-03-31

申请号：US515595

申请日：1990-04-27

申请人： Mehmet Ozturk ,  Jimmie Wortman

发明人： Mehmet Ozturk ,  Jimmie Wortman

IPC分类号： H01L21/28 ,  H01L29/49

CPC分类号： H01L29/4925 ,  H01L21/2807

摘要： The invention is a method of depositing a layer of polycrystalline silicon on a silicon dioxide substrate until the layer of polycrystalline silicon is thick enough to support the deposition of germanium thereon, but while thin enough to substantially avoid the deleterious effects on the characteristics of semiconductor device structure that the deposition of polycrystalline silicon would otherwise potentially cause. The polycrystalline layer is then exposed to a germanium containing gas at a temperature below the temperature at which germanium will deposit on silicon dioxide alone while preventing native growth of silicon dioxide on the polycrystalline silicon layer, and for a time sufficient for a desired thickness of polycrystalline germanium to be deposited on the layer of polycrystalline silicon.

摘要翻译： 本发明是一种在二氧化硅衬底上沉积多晶硅层的方法，直到多晶硅层足够厚以支持其上的锗沉积，但是同时足够薄以基本上避免对半导体器件的特性的有害影响 多晶硅的沉积否则可能导致的结构。 然后将多晶层暴露于含锗气体的温度，该温度低于锗将单独沉积在二氧化硅上的温度，同时防止二氧化硅在多晶硅层上的天然生长，并且足以达到期望厚度的多晶 锗沉积在多晶硅层上。

公开(公告)号：US07265375B2

公开(公告)日：2007-09-04

申请号：US11065085

申请日：2005-02-24

申请人： Zhibo Zhang ,  Veena Misra ,  Salah M. A. Bedair ,  Mehmet Ozturk

发明人： Zhibo Zhang ,  Veena Misra ,  Salah M. A. Bedair ,  Mehmet Ozturk

IPC分类号： H01L29/12

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/02395 ,  H01L21/02463 ,  H01L21/02488 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/02642 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/125 ,  H01L29/127 ,  Y10S977/762

摘要： Methods of forming a nano-scale electronic and optoelectronic devices include forming a substrate having a semiconductor layer therein and a substrate insulating layer on the semiconductor layer. An etching template having a first array of non-photolithographically defined nano-channels extending therethrough, is formed on the substrate insulating layer. This etching template may comprise an anodized metal oxide, such as an anodized aluminum oxide (AAO) thin film. The substrate insulating layer is then selectively etched to define a second array of nano-channels therein. This selective etching step preferably uses the etching template as an etching mask to transfer the first array of nano-channels to the underlying substrate insulating layer, which may be thinner than the etching template. An array of semiconductor nano-pillars is then formed in the second array of nano-channels. The semiconductor nano-pillars in the array may have an average diameter in a range between about 8 nm and about 50 nm. The semiconductor nano-pillars are also preferably homoepitaxial or heteroepitaxial with the semiconductor layer.

摘要翻译： 形成纳米级电子和光电子器件的方法包括在其中形成其中具有半导体层的衬底和在半导体层上的衬底绝缘层。 在衬底绝缘层上形成具有非光刻限定的纳米通道的第一阵列的蚀刻模板。 该蚀刻模板可以包括阳极氧化的金属氧化物，例如阳极氧化的氧化铝（AAO）薄膜。 然后选择性地蚀刻衬底绝缘层以在其中限定纳米通道的第二阵列。 该选择蚀刻步骤优选使用蚀刻模板作为蚀刻掩模，将第一纳米通道阵列转移到下面的衬底绝缘层，其可以比蚀刻模板更薄。 然后在第二纳米通道阵列中形成半导体纳米柱阵列。 阵列中的半导体纳米柱可以具有在约8nm和约50nm之间的范围内的平均直径。 半导体纳米柱也优选与半导体层同质外延或异质外延。

公开(公告)号：US06709929B2

公开(公告)日：2004-03-23

申请号：US10178941

申请日：2002-06-24

申请人： Zhibo Zhang ,  Veena Misra ,  Salah M. A. Bedair ,  Mehmet Ozturk

发明人： Zhibo Zhang ,  Veena Misra ,  Salah M. A. Bedair ,  Mehmet Ozturk

IPC分类号： H01L21336

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/02395 ,  H01L21/02463 ,  H01L21/02488 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/02642 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/125 ,  H01L29/127 ,  Y10S977/762

摘要： Methods of forming a nano-scale electronic and optoelectronic devices include forming a substrate having a semiconductor layer therein and a substrate insulating layer on the semiconductor layer. An etching template having a first array of non-photolithographically defined nano-channels extending therethrough, is formed on the substrate insulating layer. This etching template may comprise an anodized metal oxide, such as an anodized aluminum oxide (AAO) thin film. The substrate insulating layer is then selectively etched to define a second array of nano-channels therein. This selective etching step preferably uses the etching template as an etching mask to transfer the first array of nano-channels to the underlying substrate insulating layer, which may be thinner than the etching template. An array of semiconductor nano-pillars is then formed in the second array of nano-channels. The semiconductor nano-pillars in the array may have an average diameter in a range between about 8 nm and about 50 nm. The semiconductor nano-pillars are also preferably homoepitaxial or heteroepitaxial with the semiconductor layer.

摘要翻译： 形成纳米级电子和光电子器件的方法包括在其中形成其中具有半导体层的衬底和在半导体层上的衬底绝缘层。 在衬底绝缘层上形成具有非光刻限定的纳米通道的第一阵列的蚀刻模板。 该蚀刻模板可以包括阳极氧化的金属氧化物，例如阳极氧化的氧化铝（AAO）薄膜。 然后选择性地蚀刻衬底绝缘层以在其中限定纳米通道的第二阵列。 该选择蚀刻步骤优选使用蚀刻模板作为蚀刻掩模，将第一纳米通道阵列转移到下面的衬底绝缘层，其可以比蚀刻模板更薄。 然后在第二纳米通道阵列中形成半导体纳米柱阵列。 阵列中的半导体纳米柱可以具有在约8nm和约50nm之间的范围内的平均直径。 半导体纳米柱也优选与半导体层同质外延或异质外延。

公开(公告)号：US5089872A

公开(公告)日：1992-02-18

申请号：US515589

申请日：1990-04-27

申请人： Mehmet Ozturk ,  Jimmie Wortman ,  Douglas Grider

发明人： Mehmet Ozturk ,  Jimmie Wortman ,  Douglas Grider

IPC分类号： H01L21/285 ,  H01L29/423 ,  H01L29/45

CPC分类号： H01L29/456 ,  H01L21/28525 ,  H01L29/41783 ,  H01L29/78 ,  H01L2924/0002

摘要： The invention is a method of selectively forming contacts on ultra shallow source and drain junctions. The method comprises forming a gate structure that defines a gate on a silicon substrate, portions of which are covered with a layer of silicon dioxide while the portions adjacent the gate form a silicon surface. The gate structure includes a surface material upon which germanium will not deposit at a temperature that is otherwise high enough to cause germanium to deposit from a germanium containing gas onto a silicon surface, but that is lower than the temperature at which germanium will deposit on the gate surface material. A source and drain are formed in the silicon substrate in the portions adjacent the gate by adding dopant atoms and in which the source and drain are separated by an active region of the silicon substrate defined by the gate structure. The substrate is then exposed to a germanium containing gas at a temperature high enough to cause the germanium to deposit from the germanium containing gas into the silicon surface but lower than the temperature at which the germanium will deposit on the gate structure surface material. The result is self-aligned germanium contacts to the source and the drain. The method can further comprise selectively depositing a metal on the germanium and annealing the deposit to form a germanide compound from the reaction between the deposited germanium and the deposited metal.

摘要翻译： 本发明是在超浅源极和漏极结上选择性地形成接触的方法。 该方法包括形成限定硅衬底上的栅极的栅极结构，其一部分被二氧化硅层覆盖，而与栅极相邻的部分形成硅表面。 栅极结构包括表面材料，锗不会在其上高度足够沉积以使锗从含锗气体沉积到硅表面上的温度沉积，但是低于锗沉积在硅表面上的温度 门表面材料。 源极和漏极通过添加掺杂剂原子在与栅极相邻的部分中的硅衬底中形成，其中源极和漏极由栅极结构限定的硅衬底的有源区域分开。 然后将衬底在足够高的温度下暴露于含锗气体，以使锗从含锗气体沉积到硅表面中，但低于锗将沉积在栅极结构表面材料上的温度。 结果是自对准的锗接触源和漏极。 该方法还可以包括选择性地在锗上沉积金属并退火沉积物以从沉积的锗和沉积的金属之间的反应形成锗化合物。