公开(公告)号：US20060017161A1

公开(公告)日：2006-01-26

申请号：US11186964

申请日：2005-07-22

申请人： Jae-Sik Chung ,  Se-Young Jeong ,  Dong-Hyeon Jang

发明人： Jae-Sik Chung ,  Se-Young Jeong ,  Dong-Hyeon Jang

IPC分类号： H01L21/44 ,  H01L23/48

CPC分类号： H01L21/76838 ,  H01L23/3114 ,  H01L23/3157 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/062 ,  H05K3/108 ,  H05K3/244 ,  H05K3/388 ,  H05K2203/0505 ,  H05K2203/0597 ,  H01L2924/00 ,  H01L2924/00014

摘要： An apparatus and method for manufacturing a semiconductor package are disclosed. The apparatus may include at least a semiconductor chip having input/output (I/O) pads arranged on a surface thereof, a first dielectric layer formed on the surface of the semiconductor chip which may expose the I/O pads, a seed metal layer selectively formed on the first dielectric layer and the I/O pads, re-routing lines formed on the seed metal layer and electrically coupled to the I/O pads, a protective coating layer on side surfaces and an upper surface of each re-routing line, a second dielectric layer formed on the first dielectric layer which may cover the re-routing lines surrounded with the protective coating layer, and solder balls formed on the respective pads and electrically coupled to the re-routing lines.

摘要翻译： 公开了一种用于制造半导体封装的装置和方法。 该装置可以包括至少一个具有布置在其表面上的输入/输出（I / O）焊盘的半导体芯片，形成在半导体芯片的可能暴露I / O焊盘的表面上的第一介电层，种子金属层 选择性地形成在第一电介质层和I / O焊盘上，形成在种子金属层上并电耦合到I / O焊盘的再布线，在每个重新路由的侧表面上的保护涂层和上表面 形成在第一电介质层上的第二电介质层，其可以覆盖被保护涂层包围的重路由线，以及形成在相应焊盘上并电耦合到重路由线的焊球。

公开(公告)号：US07537959B2

公开(公告)日：2009-05-26

申请号：US11889400

申请日：2007-08-13

申请人： Kang-Wook Lee ,  Gu-Sung Kim ,  Dong-Hyeon Jang ,  Seung-Duk Baek ,  Jae-Sik Chung

发明人： Kang-Wook Lee ,  Gu-Sung Kim ,  Dong-Hyeon Jang ,  Seung-Duk Baek ,  Jae-Sik Chung

IPC分类号： H01L21/00 ,  H01L21/26 ,  H01L21/44 ,  H01L29/40

CPC分类号： H01L25/50 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/48 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05556 ,  H01L2224/05569 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  Y02P80/30 ,  Y10S438/977 ,  Y10T436/104998 ,  Y10T436/108331 ,  Y10T436/17 ,  Y10T436/175383 ,  H01L2224/81 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A chip stack package is manufactured at a wafer level by forming connection vias in the scribe lanes adjacent the chips and connecting the device chip pads to the connection vias using rerouting lines. A lower chip is then attached and connected to a substrate, which may be a test wafer, and an upper chip is attached and connected to the lower chip, the electrical connections being achieved through their respective connection vias. In addition to the connection vias, the chip stack package may include connection bumps formed between vertically adjacent chips and/or the lower chip and the substrate. The preferred substrate is a test wafer that allows the attached chips to be tested, and replaced if faulty, thereby ensuring that each layer of stacked chips includes only “known-good die” before the next layer of chips is attached thereby increasing the production rate and improving the yield.

摘要翻译： 通过在与芯片相邻的划线中形成连接通孔并且使用重新布线将连接器件芯片焊盘连接到连接通孔，在晶片级制造芯片堆叠封装。 然后将下部芯片连接并连接到可以是测试晶片的衬底，并且上部芯片被附接并连接到下部芯片，电连接通过它们各自的连接通孔来实现。 除了连接通孔之外，芯片堆叠封装可以包括在垂直相邻的芯片和/或下部芯片和衬底之间形成的连接凸块。 优选的基板是测试晶片，其允许附接的芯片被测试并且如果有故障则被替换，从而确保每层堆叠的芯片仅在连接下一层芯片之前仅包括“已知的芯片”，从而提高生产率 并提高产量。

公开(公告)号：US20070281374A1

公开(公告)日：2007-12-06

申请号：US11889400

申请日：2007-08-13

申请人： Kang-Wook Lee ,  Gu-Sung Kim ,  Dong-Hyeon Jang ,  Seung-Duk Baek ,  Jae-Sik Chung

发明人： Kang-Wook Lee ,  Gu-Sung Kim ,  Dong-Hyeon Jang ,  Seung-Duk Baek ,  Jae-Sik Chung

IPC分类号： H01L21/66 ,  H01L21/58

CPC分类号： H01L25/50 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/48 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05556 ,  H01L2224/05569 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  Y02P80/30 ,  Y10S438/977 ,  Y10T436/104998 ,  Y10T436/108331 ,  Y10T436/17 ,  Y10T436/175383 ,  H01L2224/81 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A chip stack package is manufactured at a wafer level by forming connection vias in the scribe lanes adjacent the chips and connecting the device chip pads to the connection vias using rerouting lines. A lower chip is then attached and connected to a substrate, which may be a test wafer, and an upper chip is attached and connected to the lower chip, the electrical connections being achieved through their respective connection vias. In addition to the connection vias, the chip stack package may include connection bumps formed between vertically adjacent chips and/or the lower chip and the substrate. The preferred substrate is a test wafer that allows the attached chips to be tested, and replaced if faulty, thereby ensuring that each layer of stacked chips includes only “known-good die” before the next layer of chips is attached thereby increasing the production rate and improving the yield.

公开(公告)号：US20090209063A1

公开(公告)日：2009-08-20

申请号：US12385855

申请日：2009-04-22

申请人： Kang-Wook Lee ,  Gu-Sung Kim ,  Dong-Hyeon Jang ,  Seung-Duk Baek ,  Jae-sik Chung

发明人： Kang-Wook Lee ,  Gu-Sung Kim ,  Dong-Hyeon Jang ,  Seung-Duk Baek ,  Jae-sik Chung

IPC分类号： H01L21/50 ,  H01L21/768

CPC分类号： H01L25/50 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/48 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05556 ,  H01L2224/05569 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  Y02P80/30 ,  Y10S438/977 ,  Y10T436/104998 ,  Y10T436/108331 ,  Y10T436/17 ,  Y10T436/175383 ,  H01L2224/81 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method for manufacturing chip stack packages may include: providing at least two wafers, each wafer having a plurality of chips, and scribe lanes formed between and separating adjacent chips; forming a plurality of via holes in peripheral portions of the scribe lanes; forming connection vias by filling the via holes; establishing electrical connections between the chip pads and corresponding connection vias; removing material from the back sides of the wafers to form thinned wafers; separating the thinned wafers into individual chips by removing a central portion of each scribe lane; attaching a first plurality of individual chips to a test wafer; attaching a second plurality of individual chips to the first plurality of individual chips to form a plurality of chip stack structures; encapsulating the plurality of chip stack structures; and separating the plurality of chip stack structures to form individual chip stack packages.

摘要翻译： 用于制造芯片堆叠封装的方法可以包括：提供至少两个晶片，每个晶片具有多个芯片，以及在相邻芯片之间形成并分隔相邻芯片的划线; 在划线的周边部分形成多个通孔; 通过填充通孔形成连接通孔; 建立芯片焊盘和相应的连接通孔之间的电连接; 从晶片的背面去除材料以形成薄的晶片; 通过去除每个划线的中心部分将薄的晶片分离成单独的芯片; 将第一多个独立芯片附接到测试晶片; 将第二多个独立芯片附接到所述第一多个独立芯片以形成多个芯片堆叠结构; 封装所述多个芯片堆叠结构; 以及分离所述多个芯片堆叠结构以形成单独的芯片堆叠封装。

公开(公告)号：US07205660B2

公开(公告)日：2007-04-17

申请号：US11186763

申请日：2005-07-22

申请人： Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

发明人： Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

IPC分类号： H01L23/48

CPC分类号： H01L23/3114 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02165 ,  H01L2224/02335 ,  H01L2224/02351 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/05569 ,  H01L2224/10125 ,  H01L2224/13006 ,  H01L2224/13011 ,  H01L2224/13018 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05599

摘要： A wafer level chip scale package may have a gap provided between a solder bump and a bump land. The gap may be filled with a gas. A method of manufacturing a wafer level chip scale package may involve forming a redistribution line having a first opening, forming a seed metal layer having a second opening including an undercut portion, and forming the gap using the first and the second openings.

公开(公告)号：US08368231B2

公开(公告)日：2013-02-05

申请号：US13154165

申请日：2011-06-06

申请人： Kang-Wook Lee ,  Gu-Sung Kim ,  Dong-Hyeon Jang ,  Seung-Duk Baek ,  Jae-Sik Chung

发明人： Kang-Wook Lee ,  Gu-Sung Kim ,  Dong-Hyeon Jang ,  Seung-Duk Baek ,  Jae-Sik Chung

IPC分类号： H01L23/48

CPC分类号： H01L25/50 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/48 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05556 ,  H01L2224/05569 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  Y02P80/30 ,  Y10S438/977 ,  Y10T436/104998 ,  Y10T436/108331 ,  Y10T436/17 ,  Y10T436/175383 ,  H01L2224/81 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method for manufacturing chip stack packages may include: providing at least two wafers, each wafer having a plurality of chips, and scribe lanes formed between and separating adjacent chips; forming a plurality of via holes in peripheral portions of the scribe lanes; forming connection vias by filling the via holes; establishing electrical connections between the chip pads and corresponding connection vias; removing material from the back sides of the wafers to form thinned wafers; separating the thinned wafers into individual chips by removing a central portion of each scribe lane; attaching a first plurality of individual chips to a test wafer; attaching a second plurality of individual chips to the first plurality of individual chips to form a plurality of chip stack structures; encapsulating the plurality of chip stack structures; and separating the plurality of chip stack structures to form individual chip stack packages.

公开(公告)号：US20110237004A1

公开(公告)日：2011-09-29

申请号：US13154165

申请日：2011-06-06

申请人： Kang-Wook Lee ,  Gu-Sung Kim ,  Dong-Hyeon Jang ,  Seung-Duk Baek ,  Jae-Sik Chung

发明人： Kang-Wook Lee ,  Gu-Sung Kim ,  Dong-Hyeon Jang ,  Seung-Duk Baek ,  Jae-Sik Chung

IPC分类号： H01L21/66

CPC分类号： H01L25/50 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/48 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05556 ,  H01L2224/05569 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  Y02P80/30 ,  Y10S438/977 ,  Y10T436/104998 ,  Y10T436/108331 ,  Y10T436/17 ,  Y10T436/175383 ,  H01L2224/81 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method for manufacturing chip stack packages may include: providing at least two wafers, each wafer having a plurality of chips, and scribe lanes formed between and separating adjacent chips; forming a plurality of via holes in peripheral portions of the scribe lanes; forming connection vias by filling the via holes; establishing electrical connections between the chip pads and corresponding connection vias; removing material from the back sides of the wafers to form thinned wafers; separating the thinned wafers into individual chips by removing a central portion of each scribe lane; attaching a first plurality of individual chips to a test wafer; attaching a second plurality of individual chips to the first plurality of individual chips to form a plurality of chip stack structures; encapsulating the plurality of chip stack structures; and separating the plurality of chip stack structures to form individual chip stack packages.

摘要翻译： 用于制造芯片堆叠封装的方法可以包括：提供至少两个晶片，每个晶片具有多个芯片，以及在相邻芯片之间形成并分隔相邻芯片的划线; 在划线的周边部分形成多个通孔; 通过填充通孔形成连接通孔; 建立芯片焊盘和相应的连接通孔之间的电连接; 从晶片的背面去除材料以形成薄的晶片; 通过去除每个划线的中心部分将薄的晶片分离成单独的芯片; 将第一多个独立芯片附接到测试晶片; 将第二多个独立芯片附接到所述第一多个独立芯片以形成多个芯片堆叠结构; 封装所述多个芯片堆叠结构; 以及分离所述多个芯片堆叠结构以形成单独的芯片堆叠封装。

公开(公告)号：US07977156B2

公开(公告)日：2011-07-12

申请号：US12385855

申请日：2009-04-22

申请人： Kang-Wook Lee ,  Gu-Sung Kim ,  Dong-Hyeon Jang ,  Seung-Duk Baek ,  Jae-Sik Chung

发明人： Kang-Wook Lee ,  Gu-Sung Kim ,  Dong-Hyeon Jang ,  Seung-Duk Baek ,  Jae-Sik Chung

IPC分类号： H01L21/00 ,  H01L21/26 ,  H01L21/44 ,  H01L29/40

CPC分类号： H01L25/50 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/48 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05556 ,  H01L2224/05569 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  Y02P80/30 ,  Y10S438/977 ,  Y10T436/104998 ,  Y10T436/108331 ,  Y10T436/17 ,  Y10T436/175383 ,  H01L2224/81 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method for manufacturing chip stack packages may include: providing at least two wafers, each wafer having a plurality of chips, and scribe lanes formed between and separating adjacent chips; forming a plurality of via holes in peripheral portions of the scribe lanes; forming connection vias by filling the via holes; establishing electrical connections between the chip pads and corresponding connection vias; removing material from the back sides of the wafers to form thinned wafers; separating the thinned wafers into individual chips by removing a central portion of each scribe lane; attaching a first plurality of individual chips to a test wafer; attaching a second plurality of individual chips to the first plurality of individual chips to form a plurality of chip stack structures; encapsulating the plurality of chip stack structures; and separating the plurality of chip stack structures to form individual chip stack packages.

摘要翻译： 用于制造芯片堆叠封装的方法可以包括：提供至少两个晶片，每个晶片具有多个芯片，以及在相邻芯片之间形成并分隔相邻芯片的划线; 在划线的周边部分形成多个通孔; 通过填充通孔形成连接通孔; 建立芯片焊盘和相应的连接通孔之间的电连接; 从晶片的背面去除材料以形成薄的晶片; 通过去除每个划线的中心部分将薄的晶片分离成单独的芯片; 将第一多个独立芯片附接到测试晶片; 将第二多个独立芯片附接到所述第一多个独立芯片以形成多个芯片堆叠结构; 封装所述多个芯片堆叠结构; 以及分离所述多个芯片堆叠结构以形成单独的芯片堆叠封装。

公开(公告)号：US07312143B2

公开(公告)日：2007-12-25

申请号：US11717691

申请日：2007-03-14

申请人： Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

发明人： Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

IPC分类号： H01L23/48

CPC分类号： H01L23/3114 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02165 ,  H01L2224/02335 ,  H01L2224/02351 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/05569 ,  H01L2224/10125 ,  H01L2224/13006 ,  H01L2224/13011 ,  H01L2224/13018 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05599

摘要： A wafer level chip scale package may have a gap provided between a solder bump and a bump land. The gap may be filled with a gas. A method of manufacturing a wafer level chip scale package may involve forming a redistribution line having a first opening, forming a seed metal layer having a second opening including an undercut portion, and forming the gap using the first and the second openings.

摘要翻译： 晶片级芯片级封装可以具有设置在焊料凸块和凸起焊盘之间的间隙。 间隙可以填充气体。 制造晶片级芯片级封装的方法可以包括形成具有第一开口的再分配线，形成具有包括底切部分的第二开口的种子金属层，以及使用第一和第二开口形成间隙。

公开(公告)号：US20060214293A1

公开(公告)日：2006-09-28

申请号：US11186763

申请日：2005-07-22

申请人： Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

发明人： Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

IPC分类号： H01L21/44 ,  H01L23/48

CPC分类号： H01L23/3114 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02165 ,  H01L2224/02335 ,  H01L2224/02351 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/05569 ,  H01L2224/10125 ,  H01L2224/13006 ,  H01L2224/13011 ,  H01L2224/13018 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05599

摘要： A wafer level chip scale package may have a gap provided between a solder bump and a bump land. The gap may be filled with a gas. A method of manufacturing a wafer level chip scale package may involve forming a redistribution line having a first opening, forming a seed metal layer having a second opening including an undercut portion, and forming the gap using the first and the second openings.

摘要翻译： 晶片级芯片级封装可以具有设置在焊料凸块和凸起焊盘之间的间隙。 间隙可以填充气体。 制造晶片级芯片级封装的方法可以包括形成具有第一开口的再分配线，形成具有包括底切部分的第二开口的种子金属层，以及使用第一和第二开口形成间隙。