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公开(公告)号：US5600257A
公开(公告)日：1997-02-04
申请号：US513057
申请日：1995-08-09
CPC分类号： G01R1/07385 , G01R1/07314 , G01R31/2889 , G01R31/2863 , G01R31/2879 , G01R31/2886
摘要： An apparatus and a method for simultaneously testing or burning in all the integrated circuit chips on a product wafer. The apparatus comprises a glass ceramic carrier having test chips and means for connection to pads of a large number of chips on a product wafer. Voltage regulators on the test chips provide an interface between a power supply and power pads on the product chips, at least one voltage regulator for each product chip. The voltage regulators provide a specified Vdd voltage to the product chips, whereby the Vdd voltage is substantially independent of current drawn by the product chips. The voltage regulators or other electronic means limit current to any product chip if it has a short. The voltage regulator circuit may be gated and variable and it may have sensor lines extending to the product chip. The test chips can also provide test functions such as test patterns and registers for storing test results.
摘要翻译： 用于在产品晶片上的所有集成电路芯片中同时测试或燃烧的装置和方法。 该装置包括具有测试芯片的玻璃陶瓷载体和用于连接到产品晶片上的大量芯片的焊盘的装置。 测试芯片上的电压调节器提供电源和产品芯片上的电源接口之间的接口，每个产品芯片至少有一个电压调节器。 电压调节器向产品芯片提供指定的Vdd电压，由此Vdd电压基本上与产品芯片所消耗的电流无关。 电压调节器或其他电子装置将电流限制在任何产品芯片上。 电压调节器电路可以是门控和可变的，并且其可以具有延伸到产品芯片的传感器线路。 测试芯片还可以提供测试功能，例如测试模式和用于存储测试结果的寄存器。
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2.发明授权Circuitry and methodology to establish correlation between gate dielectric test site reliability and product gate reliability 失效电路和方法建立栅介质测试点可靠性与产品门可靠性之间的相关性公开(公告)号：US07298161B2
公开(公告)日：2007-11-20
申请号：US11088953
申请日：2005-03-24
申请人： Kerry Bernstein , Ronald J. Bolam , Edward J. Nowak , Alvin W. Strong , Jody J. Van Horn , Ernest Y. Wu
发明人： Kerry Bernstein , Ronald J. Bolam , Edward J. Nowak , Alvin W. Strong , Jody J. Van Horn , Ernest Y. Wu
IPC分类号： G01R31/26
CPC分类号： G01R31/2855
摘要： A method and system for predicting gate reliability. The method comprises the steps of stressing a gate dielectric test site to obtain gate dielectric test site data and using the test site data to predict gate reliability. Preferably, the test structure and the product structure are integrated in such a manner that a test site occupies some of the product area and the product itself occupies the remainder of the product area. A preferred methodology, more specifically, is as follows: (1) Test structures at start both in parallel stress mode and in ring oscillator or “product” mode; (2) Analyze the breakdown data as per the present state of the art for each of the areas based on the parallel stress mode; (3) Combine the above breakdown distributions using the area scaling to improve the confidence bounds of the Weibull slope of the cumulative distribution function; (4) Test the ring oscillators in the product mode to determine how many of the stress fails are also product fails as defined by an operational degradation; (5) Subdivide the failures to determine the relationship between the first fail, and the second fail, and the nth fail; (6) Investigate which stress fail, if not the first stress fail, is more likely to cause a product fail as defined by operational degradation; and (7) Based on the subdivision in step 5 and the results in step 6, make projection based on that fail which is most likely to cause fail. The methodology as outlined above bridges between dielectric stress fails and product degradation both in the case of each stress fail causing a product degradation, as well as in the case where more than one stress fail occurs before any product degradation occurs. And this relationship can be quantified.
摘要翻译： 一种用于预测门可靠性的方法和系统。 该方法包括以下步骤：施加栅极电介质测试点以获得栅极介电测试点数据，并使用测试点数据来预测栅极的可靠性。 优选地，测试结构和产品结构以这样的方式集成，使得测试位置占据产品区域中的一些，并且产品本身占据产品区域的其余部分。 更具体地说，优选的方法如下：（1）并联应力模式和环形振荡器或“产品”模式下的测试结构; （2）根据平行应力模式分析每个区域的现有技术状况; （3）使用面积缩放结合上述分解分布，以提高累积分布函数的威布尔斜率的置信范围; （4）在产品模式下测试环形振荡器，以确定应力失效的数量是否也是由操作退化定义的产品故障; （5）细分失败，确定第一个失败与第二个失败之间的关系，第n个失败; （6）调查哪些压力失败，如果不是第一次压力失败，更有可能导致产品按作业退化所定义的失效; 和（7）基于步骤5中的细分和步骤6中的结果，基于最可能导致失败的失败进行投影。 如上所述的方法在介电应力失效和产物退化两者之间，在每个应力失效导致产物降解的情况下，以及在任何产物降解发生之前发生多于一个应力失效的情况下。 这种关系可以量化。
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公开(公告)号：US07000162B2
公开(公告)日：2006-02-14
申请号：US09682233
申请日：2001-08-08
CPC分类号： G01R31/2856 , G01R31/2879 , H01L22/34
摘要： Disclosed is an integrated circuit device, comprising: a first power rail for supplying power to first latch and a circuit during a first clock phase; a second power rail for supplying power to a second latch during a second clock phase; and the circuit coupled between an output of the first latch and an input of the second latch.
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4.发明授权Circuitry and methodology to establish correlation between gate dielectric test site reliability and product gate reliability 失效电路和方法建立栅介质测试点可靠性与产品门可靠性之间的相关性公开(公告)号：US06891359B2
公开(公告)日：2005-05-10
申请号：US10248506
申请日：2003-01-24
申请人： Kerry Bernstein , Ronald J. Bolam , Edward J. Nowak , Alvin W. Strong , Jody J. Van Horn , Ernest Y. Wu
发明人： Kerry Bernstein , Ronald J. Bolam , Edward J. Nowak , Alvin W. Strong , Jody J. Van Horn , Ernest Y. Wu
CPC分类号： G01R31/2855
摘要： A method and system for predicting gate reliability. The method comprises the steps of stressing a gate dielectric test site to obtain gate dielectric test site data and using the test site data to predict gate reliability. Preferably, the test structure and the product structure are integrated in such a manner that a test site occupies some of the product area and the product itself occupies the remainder of the product area. A preferred methodology, more specifically, is as follows: (1) Test structures at start both in parallel stress mode and in ring oscillator or “product” mode; (2) Analyze the breakdown data as per the present state of the art for each of the areas based on the parallel stress mode; (3) Combine the above breakdown distributions using the area scaling to improve the confidence bounds of the Weibull slope of the cumulative distribution function; (4) Test the ring oscillators in the product mode to determine how many of the stress fails are also product fails as defined by an operational degradation; (5) Subdivide the failures to determine the relationship between the first fail, and the second fail, and the nth fail; (6) Investigate which stress fail, if not the first stress fail, is more likely to cause a product fail as defined by operational degradation; and (7) Based on the subdivision in step 5 and the results in step 6, make projection based on that fail which is most likely to cause fail. The methodology as outlined above bridges between dielectric stress fails and product degradation both in the case of each stress fail causing a product degradation, as well as in the case where more than one stress fail occurs before any product degradation occurs. And this relationship can be quantified.
摘要翻译： 一种用于预测门可靠性的方法和系统。 该方法包括以下步骤：施加栅极电介质测试点以获得栅极介电测试点数据，并使用测试点数据来预测栅极的可靠性。 优选地，测试结构和产品结构以这样的方式集成，使得测试位置占据产品区域中的一些，并且产品本身占据产品区域的其余部分。 更具体地说，优选的方法如下：（1）并联应力模式和环形振荡器或“产品”模式下的测试结构; （2）根据平行应力模式分析每个区域的现有技术状况; （3）使用面积缩放结合上述分解分布，以提高累积分布函数的威布尔斜率的置信范围; （4）在产品模式下测试环形振荡器，以确定应力失效的数量是否也是由操作退化定义的产品故障; （5）细分故障，确定第一个失败和第二个失败之间的关系，并且n th 失败; （6）调查哪些压力失败，如果不是第一次压力失败，更有可能导致产品按作业退化所定义的失效; 和（7）基于步骤5中的细分和步骤6中的结果，基于最可能导致失败的失败进行投影。 如上所述的方法在介电应力失效和产物退化两者之间，在每个应力失效导致产物降解的情况下，以及在任何产物降解发生之前发生多于一个应力失效的情况下。 这种关系可以量化。
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公开(公告)号：US09152517B2
公开(公告)日：2015-10-06
申请号：US13091879
申请日：2011-04-21
申请人： Harold Chase , Dennis R. Conti , James M. Crafts , David L. Gardell , Andrew T. Holle , Adrian Patrascu , Jody J. Van Horn
发明人： Harold Chase , Dennis R. Conti , James M. Crafts , David L. Gardell , Andrew T. Holle , Adrian Patrascu , Jody J. Van Horn
CPC分类号： G06F11/24 , G01R31/2877 , G06F1/206 , G06F1/3203
摘要： Test equipment provides interrupt capability to automatic testing as a means of actively controlling temperature of the device under test. A processor coupled to memory is responsive to computer-executable instructions contained in the memory. A test socket is coupled to a device under test and coupled to the processor. The processor is configured to interrupt an application pattern running on the device under test. In response to interrupting the application pattern, the processor is configured to cause a control pattern to run on the device under test and then cause the application pattern to restart running from the point of interruption on the device under test.
摘要翻译： 测试设备提供自动测试的中断能力，作为主动控制被测设备温度的一种手段。 耦合到存储器的处理器响应包含在存储器中的计算机可执行指令。 测试插座耦合到被测设备并耦合到处理器。 处理器配置为中断在被测设备上运行的应用程序模式。 响应于中断应用模式，处理器被配置为使得控制模式在被测设备上运行，然后使应用模式从被测设备上的中断点重新启动。
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公开(公告)号：US20120272100A1
公开(公告)日：2012-10-25
申请号：US13091879
申请日：2011-04-21
申请人： Harold Chase , Dennis R. Conti , James M. Crafts , David L. Gardell , Andrew T. Holle , Adrian Patrascu , Jody J. Van Horn
发明人： Harold Chase , Dennis R. Conti , James M. Crafts , David L. Gardell , Andrew T. Holle , Adrian Patrascu , Jody J. Van Horn
IPC分类号： G06F11/07
CPC分类号： G06F11/24 , G01R31/2877 , G06F1/206 , G06F1/3203
摘要： Test equipment provides interrupt capability to automatic testing as a means of actively controlling temperature of the device under test. A processor coupled to memory is responsive to computer-executable instructions contained in the memory. A test socket is coupled to a device under test and coupled to the processor. The processor is configured to interrupt an application pattern running on the device under test. In response to interrupting the application pattern, the processor is configured to cause a control pattern to run on the device under test and then cause the application pattern to restart running from the point of interruption on the device under test.
摘要翻译： 测试设备提供自动测试的中断能力，作为主动控制被测设备温度的一种手段。 耦合到存储器的处理器响应包含在存储器中的计算机可执行指令。 测试插座耦合到被测设备并耦合到处理器。 处理器配置为中断在被测设备上运行的应用程序模式。 响应于中断应用模式，处理器被配置为使得控制模式在被测设备上运行，然后使应用模式从被测设备上的中断点重新启动。
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7.发明授权公开(公告)号：US06763314B2
公开(公告)日：2004-07-13
申请号：US09967550
申请日：2001-09-28
申请人： Phillip J. Nigh , Jody J. Van Horn
发明人： Phillip J. Nigh , Jody J. Van Horn
IPC分类号： G01R3100
CPC分类号： G01R19/2513
摘要： A system for modifying the power up and diagnostic procedure of systems such that the system voltage is lowered to a predetermined voltage level that has been shown to detect delay faults. The system conducts the normal procedure of power up/diagnostic routines at the described VLV condition and then logs failures to this VLV condition. Upon completion of the VLV power up, the system is shut down normally and then subsequently powered up again at the normal voltage conditions. Discrepancies between the VLV power up/diagnostics are noted in the system log and communicated appropriately.
摘要翻译： 一种用于修改系统的上电和诊断过程的系统，使得系统电压降低到已经显示为检测延迟故障的预定电压电平。 系统在上述VLV条件下执行上电/诊断例程的正常程序，然后将故障记录到该VLV条件。 在VLV上电完成后，系统正常关闭，然后在正常电压条件下再次上电。 在系统日志中记录VLV上电/诊断之间的差异并进行适当的通信。
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公开(公告)号：US06618682B2
公开(公告)日：2003-09-09
申请号：US09838996
申请日：2001-04-20
申请人： Raymond J. Bulaga , Anne E. Gattiker , John L. Harris , Phillip J. Nigh , Leo A. Noel , William J. Thibault , Jody J. Van Horn , Donald L. Wheater
发明人： Raymond J. Bulaga , Anne E. Gattiker , John L. Harris , Phillip J. Nigh , Leo A. Noel , William J. Thibault , Jody J. Van Horn , Donald L. Wheater
IPC分类号： G01N3700
CPC分类号： H01L22/20
摘要： A method and system are provided that minimize wafer or package level test time without adversely impacting yields in downstream manufacturing processes or degrading outgoing quality levels. The method provides optimization by determining, a priority, the most effective set of tests for a given lot or wafer. The invention implements a method using a processor-based system involving the integration of multiple sources of data that include: historical and realtime, product specific and lot specific, from wafer fabrication data (i.e., process measurements, defect inspections, and parametric testing), product qualification test results, physical failure analysis results and manufacturing functional test results. These various forms of data are used to determine an optimal set of tests to run using a test application sequence, on a given product to optimize test time with minimum risk to yield or product quality.
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