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    Variable resistance memory devices and methods of manufacturing the same
    1.
    发明授权
    Variable resistance memory devices and methods of manufacturing the same 有权

    公开(公告)号：US09812501B2

    公开(公告)日：2017-11-07

    申请号：US14984477

    申请日：2015-12-30

    申请人： Jin-Woo Lee ,  Youn-Seon Kang ,  Seung-Jae Jung ,  Hyun-Su Ju ,  Masayuki Terai

    发明人： Jin-Woo Lee ,  Youn-Seon Kang ,  Seung-Jae Jung ,  Hyun-Su Ju ,  Masayuki Terai

    IPC分类号： H01L27/24 ,  H01L43/08 ,  H01L43/02 ,  H01L43/12 ,  H01L45/00 ,  H01L27/22

    CPC分类号： H01L27/2463 ,  H01L27/224 ,  H01L27/2409 ,  H01L43/12 ,  H01L45/1675

    摘要： A variable resistance memory device includes a plurality of first conductive layer pattern, a plurality of second conductive layer patterns over the first conductive layer patterns, and a plurality of lower cell structures including a switching element and a variable resistance element, the lower cell structures being formed at intersections at which the first conductive layer patterns and the second conductive layer patterns overlap each other. The first conductive layer patterns, the second conductive layer patterns and the lower cell structures serves as one of a memory cell, a first dummy pattern structure and a second dummy pattern structure. The first dummy pattern structure is formed on both edge portions in the first direction, and the second conductive layer pattern of the first dummy pattern structure protrudes in the first direction from a sidewall of the lower cell structure thereunder, and the second dummy pattern structure is formed on both edge portions in the second direction, and the first conductive layer pattern of the second dummy pattern structure protrudes in the second direction from a sidewall of the lower cell structure thereon. Failures of the variable resistance memory device due to the etch residue may decrease.

    Variable resistance memory devices and methods of manufacturing the same
    2.
    发明授权
    Variable resistance memory devices and methods of manufacturing the same 有权

    公开(公告)号：US09685609B2

    公开(公告)日：2017-06-20

    申请号：US14963947

    申请日：2015-12-09

    申请人： Seung-Jae Jung ,  Youn-Seon Kang

    发明人： Seung-Jae Jung ,  Youn-Seon Kang

    IPC分类号： H01L27/24 ,  H01L45/00

    CPC分类号： H01L45/147 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/141 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16

    摘要： A variable resistance memory device includes a plurality of first conductive lines, each of the first conductive lines extends in a first direction, a plurality of second conductive lines are above the first conductive lines, and each of the second conductive lines extend in a second direction transverse to the first direction. A plurality of first memory cells are at intersections where the first and second conductive lines overlap each other, each of the first memory cells including a first variable resistance structure having a first variable resistance pattern, a first sacrificial pattern and a second variable resistance pattern sequentially stacked in the first direction on a first plane. A plurality of third conductive lines are above the second conductive lines, each of the third conductive lines extend in the first direction, and a plurality of second memory cells are at intersections where the second and the third conductive lines overlap each other. Each of the second memory cells includes a second variable resistance structure having a third variable resistance pattern, a second sacrificial pattern and a fourth variable resistance pattern sequentially stacked in the first direction on second plane.

    VARIABLE RESISTANCE MEMORY DEVICES
    3.
    发明申请
    VARIABLE RESISTANCE MEMORY DEVICES 有权
    可变电阻存储器件

    公开(公告)号：US20150214478A1

    公开(公告)日：2015-07-30

    申请号：US14457439

    申请日：2014-08-12

    申请人： Jung-Moo Lee ,  Youn-Seon Kang ,  Seung-Jae Jung ,  Jung-Dal Choi

    发明人： Jung-Moo Lee ,  Youn-Seon Kang ,  Seung-Jae Jung ,  Jung-Dal Choi

    IPC分类号： H01L45/00 ,  H01L27/24

    CPC分类号： H01L45/1233 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1675

    摘要： A variable resistance memory device includes a plurality of first conductive lines, a plurality of second conductive lines, a plurality of memory cells, a plurality of first air gaps and a plurality of second air gaps. The first conductive line extends in a first direction. The second conductive line is over the first conductive line and extends in a second direction crossing the first direction. The memory cell includes a variable resistance device. The memory cell is located at an intersection region of the first conductive line and the second conductive line. The first air gap extends in the first direction between the memory cells. The second air gap extends in the second direction between the memory cells.

    摘要翻译： 可变电阻存储器件包括多个第一导线，多个第二导线，多个存储单元，多个第一气隙和多个第二气隙。 第一导线沿第一方向延伸。 第二导线在第一导线上方并且沿与第一方向交叉的第二方向延伸。 存储单元包括可变电阻器件。 存储单元位于第一导线和第二导线的交叉区域。 第一气隙在存储单元之间沿第一方向延伸。 第二气隙沿第二方向在存储单元之间延伸。

    Variable resistance memory devices and methods of manufacturing the same
    4.
    发明授权
    Variable resistance memory devices and methods of manufacturing the same 有权
    可变电阻存储器件及其制造方法

    公开(公告)号：US09373664B2

    公开(公告)日：2016-06-21

    申请号：US14682506

    申请日：2015-04-09

    申请人： Dong-Jun Seong ,  Youn-Seon Kang ,  Seung-Jae Jung ,  Jung-Dal Choi

    发明人： Dong-Jun Seong ,  Youn-Seon Kang ,  Seung-Jae Jung ,  Jung-Dal Choi

    IPC分类号： H01L29/06 ,  H01L27/24 ,  H01L45/00

    CPC分类号： H01L27/2463 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

    摘要： A variable resistance memory device, and methods of manufacturing the same, include a plurality of first conductive structures extending in a first direction, a plurality of second conductive structures extending in a second direction crossing the first direction over the first conductive structures, the second conductive structures, and a plurality of memory cells that are formed at intersections at which the first conductive structures and the second conductive structures overlap each other, and each includes a selection element and a variable resistance element sequentially stacked. An upper surface of each of the first conductive structures has a width in the second direction less than a width of a bottom surface of each of the selection elements.

    摘要翻译： 可变电阻存储器件及其制造方法包括沿第一方向延伸的多个第一导电结构，沿与第一导电结构相交的第一方向的第二方向延伸的多个第二导电结构，第二导电 结构和形成在第一导电结构和第二导电结构彼此重叠的交点处的多个存储单元，并且每个存储单元包括依次堆叠的选择元件和可变电阻元件。 每个第一导电结构的上表面在第二方向上的宽度小于每个选择元件的底表面的宽度。

    Resistive memory device and method of operating resistive memory device
    5.
    发明授权
    Resistive memory device and method of operating resistive memory device 有权
    电阻式存储器件和操作电阻式存储器件的方法

    公开(公告)号：US09450025B2

    公开(公告)日：2016-09-20

    申请号：US14736525

    申请日：2015-06-11

    申请人： Seung-Jae Jung ,  Youn-Seon Kang ,  Jung-Dal Choi

    发明人： Seung-Jae Jung ,  Youn-Seon Kang ,  Jung-Dal Choi

    IPC分类号： H01L27/24 ,  H01L45/00 ,  H01L27/22

    CPC分类号： H01L27/2463 ,  H01L27/224 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/1675

    摘要： A resistive memory device includes a plurality of memory cell pillars arranged in a line in one direction and each having a memory layer and a top electrode layer connected to the memory layer, a top conductive line having a plurality of protrusions extending downwardly and between which pockets in the bottom of the top conductive line are defined, and a plurality of insulating pillars. The protrusions of the top conductive line face and are electrically connected to the memory cell pillars, respectively, so as to be electrically connected to the memory layer through the top electrode layer of the memory cell pillar. The insulating pillars extend from insulating spaces, between side wall surfaces of the memory layers and top electrode layers of the memory cell pillars, into the pockets in the bottom of the top conductive line.

    摘要翻译： 电阻式存储器件包括沿一个方向排列成一行的多个存储器单元柱，每个存储单元柱具有连接到存储层的存储层和顶部电极层，顶部导电线具有向下延伸的多个突起， 在顶部导线的底部被限定，以及多个绝缘柱。 上导电线面的突起分别电连接到存储单元柱，以便通过存储单元柱的顶电极电连接到存储层。 绝缘柱从记忆层的侧壁表面和存储单元柱的顶部电极层之间的绝缘空间延伸到顶部导电线的底部中的凹穴中。

    DISPLAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME
    7.
    发明申请
    DISPLAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
    显示基板及其制造方法

    公开(公告)号：US20090251656A1

    公开(公告)日：2009-10-08

    申请号：US12391541

    申请日：2009-02-24

    申请人： Bong-Kyu Shin ,  Seung-Jae Jung ,  Sang-Uk Lim ,  Sang-Woo Whangbo ,  Jae-Ho Choi ,  Hwa-Yeul Oh ,  Yong-Mo Choi

    发明人： Bong-Kyu Shin ,  Seung-Jae Jung ,  Sang-Uk Lim ,  Sang-Woo Whangbo ,  Jae-Ho Choi ,  Hwa-Yeul Oh ,  Yong-Mo Choi

    IPC分类号： G02F1/1333 ,  H05K3/00

    CPC分类号： G02F1/133345 ,  G02F1/13454

    摘要： A display substrate includes a soda-lime glass substrate, a barrier pattern, and first, second and third conductive patterns. The soda-lime glass substrate has a pixel area. The first conductive pattern includes a gate line formed on the soda-lime glass substrate and from a first conductive layer. The barrier pattern is formed between the first conductive pattern and the soda-lime glass substrate. The second conductive pattern includes a data line crossing the gate line. The data line is formed on the first conductive pattern and from a second conductive layer. The third conductive pattern includes a pixel electrode formed in the pixel area of the soda-lime glass substrate. The pixel electrode is formed on the second conductive pattern and from a third conductive layer.

    摘要翻译： 显示基板包括钠钙玻璃基板，阻挡图案以及第一，第二和第三导电图案。 钠钙玻璃基板具有像素面积。 第一导电图案包括形成在钠钙玻璃基板上和从第一导电层形成的栅极线。 在第一导电图案和钠钙玻璃基板之间形成阻挡图案。 第二导电图案包括与栅极线交叉的数据线。 数据线形成在第一导电图案上和从第二导电层形成。 第三导电图案包括形成在钠钙玻璃基板的像素区域中的像素电极。 像素电极形成在第二导电图案上并由第三导电层形成。

    Inductively coupled plasma apparatus
    9.
    发明授权
    Inductively coupled plasma apparatus 有权
    电感耦合等离子体装置

    公开(公告)号：US08293069B2

    公开(公告)日：2012-10-23

    申请号：US12331981

    申请日：2008-12-10

    申请人： Geun-Young Yeom ,  Kyong-Nam Kim ,  Seung-Jae Jung

    发明人： Geun-Young Yeom ,  Kyong-Nam Kim ,  Seung-Jae Jung

    IPC分类号： C23C16/00 ,  C23F1/00 ,  H01L21/306 ,  H05B31/26

    CPC分类号： H01J37/321

    摘要： A inductively coupled plasma apparatus includes reaction chamber in which a substrate is loaded, and a double comb type antenna structure including first linear antennas and second linear antennas respectively arranged horizontally to pass through the reaction chamber inside the reaction chamber. The first and second linear antenna are alternately aligned each other. First ends the first linear antennas are protruded out of the reaction chamber and coupled to each other so as to be coupled to a first induced RF power, and first ends of the second linear antennas are protruded out of the reaction chamber in opposition to the first ends of the first linear antennas and coupled to each other so as to be coupled to a second induced RF power. Plasma uniformity is improved and superior plasma uniformity is maintained by adjusting a distance between antennas according to a size of the substrate.

    摘要翻译： 电感耦合等离子体装置包括其中装载有基板的反应室，以及包括分别水平布置以通过反应室内的反应室的第一线性天线和第二线性天线的双梳型天线结构。 第一和第二线性天线彼此交替地对准。 首先，第一线性天线从反应室突出并彼此耦合，以便耦合到第一感应RF功率，并且第二线性天线的第一端与第一线性天线相反地突出出反应室 第一线性天线的端部并且彼此耦合，以便耦合到第二感应RF功率。 等离子体均匀性得到改善，并且通过根据基板的尺寸调节天线之间的距离来维持优异的等离子体均匀性。