公开(公告)号：US20070111385A1

公开(公告)日：2007-05-17

申请号：US11650883

申请日：2007-01-08

申请人： John Magerlein ,  Chirag Patel ,  Edmund Sprogis ,  Herbert Stoller

发明人： John Magerlein ,  Chirag Patel ,  Edmund Sprogis ,  Herbert Stoller

IPC分类号： H01L21/00 ,  H01L21/44

CPC分类号： H01L21/486 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/147 ,  H01L24/16 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68345 ,  H01L2221/68354 ,  H01L2221/68363 ,  H01L2224/05571 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2924/00012

摘要： A Silicon Based Package (SBP) is formed starting with a thick wafer, which serves as the base for the SBP, composed of silicon which has a first surface and a reverse surface which are planar. Then form an interconnection structure including metal capture structures in contact with the first surface and multilayer conductor patterns over the first surface. Form a temporary bond between the SBP and a wafer holder, with the wafer holder being a rigid structure. Thin the reverse side of the wafer to a desired thickness to form an Ultra Thin Silicon Wafer (UTSW) for the SBP. Form via holes with tapered or vertical sidewalls, which extend through the UTSW to reach the metal capture structures. Then form metal pads in the via holes which extend through the UTSW, making electrical contact to the metal capture structures. Then bond the metal pads in the via holes to pads of a carrier.

摘要翻译： 基于硅的封装（SBP）由从作为SBP的基底的厚晶片开始形成，该基板由具有平坦的第一表面和反面的硅组成。 然后形成包括与第一表面接触的金属捕获结构和在第一表面上的多层导体图案的互连结构。 在SBP和晶片保持器之间形成临时结合，晶片保持器是刚性结构。 将晶圆的反面变薄到所需的厚度，以形成用于SBP的超薄硅晶片（UTSW）。 通过具有锥形或垂直侧壁的孔形成，其延伸穿过UTSW以到达金属捕获结构。 然后在穿过UTSW的通孔中形成金属焊盘，使其与金属捕获结构电接触。 然后将通孔中的金属焊盘接合到载体的焊盘。

公开(公告)号：US20050121768A1

公开(公告)日：2005-06-09

申请号：US10729254

申请日：2003-12-05

申请人： Daniel Edelstein ,  Paul Andry ,  Leena Buchwalter ,  Jon Casey ,  Sherif Goma ,  Raymond Horton ,  Gareth Hougham ,  Michael Lane ,  Xiao Liu ,  Chirag Patel ,  Edmund Sprogis ,  Michelle Steen ,  Brian Sundlof ,  Cornelia Tsang ,  George Walker

发明人： Daniel Edelstein ,  Paul Andry ,  Leena Buchwalter ,  Jon Casey ,  Sherif Goma ,  Raymond Horton ,  Gareth Hougham ,  Michael Lane ,  Xiao Liu ,  Chirag Patel ,  Edmund Sprogis ,  Michelle Steen ,  Brian Sundlof ,  Cornelia Tsang ,  George Walker

IPC分类号： H01L21/48 ,  H01L21/768 ,  H01L23/498 ,  H01L23/48 ,  H01L21/4763

CPC分类号： H01L23/49883 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00

摘要： A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.

摘要翻译： 一种载体结构和方法，用于制造具有通孔的载流子结构，每个导通孔具有导电结构，其有效热膨胀系数小于或接近于基板的热膨胀系数，并且具有小于或等于 或者与衬底的密切匹配。 导电结构可以包括同心的通孔填充区域，其具有同心设置的不同材料，由导电材料的环形环包围的衬底材料的芯，由导电材料的环形环包围的CTE匹配的非导电材料的芯， 具有低CTE的内部空隙的导电通孔，或已经烧结或熔合的诸如金属 - 陶瓷浆料的导电复合材料的完整填充物。

公开(公告)号：US20060027934A1

公开(公告)日：2006-02-09

申请号：US11242221

申请日：2005-10-03

申请人： Daniel Edelstein ,  Paul Andry ,  Leena Buchwalter ,  Jon Casey ,  Sherif Goma ,  Raymond Horton ,  Gareth Hougham ,  Michael Lane ,  Xiao Liu ,  Chirag Patel ,  Edmund Sprogis ,  Michelle Steen ,  Brian Sundlof ,  Cornelia Tsang ,  George Walker ,  Yu-Ting Cheng ,  Kenneth Ocheltree ,  Robert Montoye

发明人： Daniel Edelstein ,  Paul Andry ,  Leena Buchwalter ,  Jon Casey ,  Sherif Goma ,  Raymond Horton ,  Gareth Hougham ,  Michael Lane ,  Xiao Liu ,  Chirag Patel ,  Edmund Sprogis ,  Michelle Steen ,  Brian Sundlof ,  Cornelia Tsang ,  George Walker ,  Yu-Ting Cheng ,  Kenneth Ocheltree ,  Robert Montoye

IPC分类号： H01L23/48

CPC分类号： H01L23/49883 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00

摘要： A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.

摘要翻译： 一种载体结构和方法，用于制造具有通孔的载流子结构，每个导通孔具有导电结构，其有效热膨胀系数小于或接近于基板的热膨胀系数，并且具有小于或等于 或者与衬底的密切匹配。 导电结构可以包括同心的通孔填充区域，其具有同心设置的不同材料，由导电材料的环形环包围的衬底材料的芯，由导电材料的环形环包围的CTE匹配的非导电材料的芯， 具有低CTE的内部空隙的导电通孔，或已经烧结或熔合的诸如金属 - 陶瓷浆料的导电复合材料的完整填充物。

公开(公告)号：US20070048896A1

公开(公告)日：2007-03-01

申请号：US11214602

申请日：2005-08-30

申请人： Paul Andry ,  Chirag Patel ,  Edmund Sprogis ,  Cornelia Tsang

发明人： Paul Andry ,  Chirag Patel ,  Edmund Sprogis ,  Cornelia Tsang

IPC分类号： H01L21/00

CPC分类号： H01L23/49833 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/13009 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/3011 ,  Y10T29/49165 ,  H01L2924/014 ,  H01L2224/05552

摘要： Conductive through vias are formed in electronic devices and electronic device carrier, such as, a silicon chip carrier. An annulus cavity is etched into the silicon carrier from the top side of the carrier and the cavity is filled with insulating material to form an isolation collar around a silicon core region. An insulating layer with at least one wiring level, having a portion in contact with the silicon core region, is formed on the top side of the carrier. Silicon is removed from the back side of the carrier sufficient to expose the distal portion of the isolation collar. The core region is etched out to expose the portion of the wiring level in contact with the silicon core region to form an empty via. The via is filled with conductive material in contact with the exposed portion of the wiring level to form a conductive through via to the wiring level. A solder bump formed, for example, from low melt C4 solder, is formed on the conductive via exposed on the carrier back side. The process acts to make the conductive via fill step independent of the via isolation step.

摘要翻译： 导电通孔形成在电子器件和电子器件载体中，例如硅芯片载体。 环状空腔从载体的顶侧蚀刻到硅载体中，并且空腔填充绝缘材料以在硅芯区域周围形成隔离环。 在载体的顶侧上形成具有至少一个布线层的绝缘层，其具有与硅芯区域接触的部分。 将硅从载体的背面移除，足以露出隔离套环的远端部分。 蚀刻芯区域以暴露与硅芯区域接触的布线层的部分以形成空通孔。 通孔填充有与布线层的暴露部分接触的导电材料，以形成导电通孔到布线层。 在载体背侧露出的导电通孔上形成例如由低熔点C4焊料形成的焊料凸块。 该过程用于使导电通孔填充步骤独立于通孔隔离步骤。

公开(公告)号：USD619069S1

公开(公告)日：2010-07-06

申请号：US29346356

申请日：2009-10-30

申请人： Chirag Patel

设计人： Chirag Patel

公开(公告)号：US07663750B2

公开(公告)日：2010-02-16

申请号：US11480287

申请日：2006-06-30

申请人： Dar Bahatt ,  Chirag Patel ,  Roy H. Tan ,  Derek Prothro

发明人： Dar Bahatt ,  Chirag Patel ,  Roy H. Tan ,  Derek Prothro

IPC分类号： G01J3/28

CPC分类号： G01N21/31 ,  G01J3/10 ,  G01J3/12 ,  G01J3/18 ,  G01J3/189 ,  G01J3/2803 ,  G01J3/2823 ,  G01J3/4406 ,  G01J2003/1204 ,  G01J2003/1208 ,  G01J2003/1213 ,  G01J2003/1226 ,  G01N21/0332 ,  G01N21/253 ,  G01N21/6428 ,  G01N21/6452 ,  G01N21/6456 ,  G01N21/76 ,  G01N2021/6421 ,  G01N2021/6432 ,  G01N2201/06113 ,  G01N2201/0621 ,  G01N2201/0697

摘要： Systems, including methods, apparatus, and algorithms, for spectrally imaging a two-dimensional array of samples.

摘要翻译： 用于对二维样本阵列进行光谱成像的系统，包括方法，装置和算法。

公开(公告)号：US06954576B2

公开(公告)日：2005-10-11

申请号：US10895685

申请日：2004-07-21

申请人： Tony Mule′ ,  Chirag Patel ,  James D. Meindl ,  Thomas K. Gaylord ,  Elias N. Glytsis ,  Kevin P. Martin ,  Stephen M. Schultz ,  Muhannad Bakir ,  Hollie Reed ,  Paul Kohl

发明人： Tony Mule′ ,  Chirag Patel ,  James D. Meindl ,  Thomas K. Gaylord ,  Elias N. Glytsis ,  Kevin P. Martin ,  Stephen M. Schultz ,  Muhannad Bakir ,  Hollie Reed ,  Paul Kohl

IPC分类号： G02B6/10 ,  G02B6/12 ,  G02B6/122 ,  G02B6/132 ,  G02B6/136 ,  G02B6/34 ,  G02B6/43

CPC分类号： G02B6/43 ,  G02B6/10 ,  G02B6/12002 ,  G02B6/1221 ,  G02B6/132 ,  G02B6/136 ,  G02B6/34 ,  G02B2006/12107

摘要： Wafer-level electronic packages having waveguides and methods of fabricating chip-level electronic packages having waveguides are disclosed. A representative chip-level electronic package includes at least one waveguide having a waveguide core. In addition, another representative chip-level electronic package includes a waveguide having an air-gap cladding layer around a portion of the waveguide core. A representative method for fabricating a chip-level electronic package includes: providing a substrate having a passivation layer disposed on the substrate; disposing a waveguide core on a portion of the passivation layer; disposing a first sacrificial layer onto at least one portion of the passivation layer and the waveguide core; disposing an overcoat layer onto the passivation layer and the first sacrificial layer; and removing the first sacrificial layer to define an air-gap cladding layer within the overcoat polymer layer and around a portion of the waveguide core.

摘要翻译： 公开了具有波导的晶片级电子封装以及制造具有波导的芯片级电子封装的方法。 代表性的芯片级电子封装包括至少一个具有波导芯的波导。 此外，另一代表性的芯片级电子封装包括在波导芯的一部分周围具有气隙包覆层的波导。 用于制造芯片级电子封装的代表性方法包括：提供具有设置在基板上的钝化层的基板; 在所述钝化层的一部分上设置波导芯; 在所述钝化层和所述波导芯的至少一部分上设置第一牺牲层; 在所述钝化层和所述第一牺牲层上设置外涂层; 以及去除所述第一牺牲层以在所述外涂层聚合物层内和所述波导芯的一部分周围限定气隙包覆层。

公开(公告)号：US08733840B2

公开(公告)日：2014-05-27

申请号：US13542816

申请日：2012-07-06

申请人： Rik Westerink ,  Armando Valdes ,  Chirag Patel ,  Timothy W. Terleski

发明人： Rik Westerink ,  Armando Valdes ,  Chirag Patel ,  Timothy W. Terleski

IPC分类号： B60N2/12 ,  B60N2/20 ,  B60N2/22

CPC分类号： B64D11/064 ,  B60N2/1625 ,  B60N2/1835 ,  B60N2/1839 ,  B60N2/2209 ,  B60N2/2222

摘要： Described are seat pan assemblies for a passenger seat having a pan frame pivotally coupled to a seat back, a seat pan pivotally coupled to the pan frame, a tilting mechanism coupled to the seat pan and the pan frame, wherein the tilting mechanism is configured to rotate the seat pan between an upright position and a sleeper position, and an automatic release mechanism, wherein the automatic release mechanism is configured to return the seat pan to an upright position when the seat back is in an upright position.

摘要翻译： 描述了一种用于乘客座椅的座椅盘组件，其具有枢转地联接到座椅靠背的平台框架，枢转地联接到平台框架的座椅平台，联接到座椅盘和摇摆框架的倾斜机构，其中倾斜机构构造成 将座椅盘在直立位置和卧铺位置之间旋转，以及自动释放机构，其中自动释放机构构造成当座椅靠背处于直立位置时将座椅底板返回到直立位置。

公开(公告)号：USD671050S1

公开(公告)日：2012-11-20

申请号：US29399516

申请日：2011-08-15

申请人： Benjamin Davidson ,  Chirag Patel

设计人： Benjamin Davidson ,  Chirag Patel

公开(公告)号：USD619525S1

公开(公告)日：2010-07-13

申请号：US29346359

申请日：2009-10-30

申请人： Chirag Patel

设计人： Chirag Patel