公开(公告)号：US20050121768A1

公开(公告)日：2005-06-09

申请号：US10729254

申请日：2003-12-05

申请人： Daniel Edelstein ,  Paul Andry ,  Leena Buchwalter ,  Jon Casey ,  Sherif Goma ,  Raymond Horton ,  Gareth Hougham ,  Michael Lane ,  Xiao Liu ,  Chirag Patel ,  Edmund Sprogis ,  Michelle Steen ,  Brian Sundlof ,  Cornelia Tsang ,  George Walker

发明人： Daniel Edelstein ,  Paul Andry ,  Leena Buchwalter ,  Jon Casey ,  Sherif Goma ,  Raymond Horton ,  Gareth Hougham ,  Michael Lane ,  Xiao Liu ,  Chirag Patel ,  Edmund Sprogis ,  Michelle Steen ,  Brian Sundlof ,  Cornelia Tsang ,  George Walker

IPC分类号： H01L21/48 ,  H01L21/768 ,  H01L23/498 ,  H01L23/48 ,  H01L21/4763

CPC分类号： H01L23/49883 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00

摘要： A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.

摘要翻译： 一种载体结构和方法，用于制造具有通孔的载流子结构，每个导通孔具有导电结构，其有效热膨胀系数小于或接近于基板的热膨胀系数，并且具有小于或等于 或者与衬底的密切匹配。 导电结构可以包括同心的通孔填充区域，其具有同心设置的不同材料，由导电材料的环形环包围的衬底材料的芯，由导电材料的环形环包围的CTE匹配的非导电材料的芯， 具有低CTE的内部空隙的导电通孔，或已经烧结或熔合的诸如金属 - 陶瓷浆料的导电复合材料的完整填充物。

公开(公告)号：US20060027934A1

公开(公告)日：2006-02-09

申请号：US11242221

申请日：2005-10-03

申请人： Daniel Edelstein ,  Paul Andry ,  Leena Buchwalter ,  Jon Casey ,  Sherif Goma ,  Raymond Horton ,  Gareth Hougham ,  Michael Lane ,  Xiao Liu ,  Chirag Patel ,  Edmund Sprogis ,  Michelle Steen ,  Brian Sundlof ,  Cornelia Tsang ,  George Walker ,  Yu-Ting Cheng ,  Kenneth Ocheltree ,  Robert Montoye

发明人： Daniel Edelstein ,  Paul Andry ,  Leena Buchwalter ,  Jon Casey ,  Sherif Goma ,  Raymond Horton ,  Gareth Hougham ,  Michael Lane ,  Xiao Liu ,  Chirag Patel ,  Edmund Sprogis ,  Michelle Steen ,  Brian Sundlof ,  Cornelia Tsang ,  George Walker ,  Yu-Ting Cheng ,  Kenneth Ocheltree ,  Robert Montoye

IPC分类号： H01L23/48

CPC分类号： H01L23/49883 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00

摘要： A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.

摘要翻译： 一种载体结构和方法，用于制造具有通孔的载流子结构，每个导通孔具有导电结构，其有效热膨胀系数小于或接近于基板的热膨胀系数，并且具有小于或等于 或者与衬底的密切匹配。 导电结构可以包括同心的通孔填充区域，其具有同心设置的不同材料，由导电材料的环形环包围的衬底材料的芯，由导电材料的环形环包围的CTE匹配的非导电材料的芯， 具有低CTE的内部空隙的导电通孔，或已经烧结或熔合的诸如金属 - 陶瓷浆料的导电复合材料的完整填充物。

公开(公告)号：US20080036084A1

公开(公告)日：2008-02-14

申请号：US11341458

申请日：2006-01-30

申请人： Leena Buchwalter ,  Paul Andry ,  Matthew Farinelli ,  Sherif Goma ,  Raymond Horton ,  Edmund Sprogis

发明人： Leena Buchwalter ,  Paul Andry ,  Matthew Farinelli ,  Sherif Goma ,  Raymond Horton ,  Edmund Sprogis

IPC分类号： H01L23/48 ,  H01L21/00

CPC分类号： H01L21/67092 ,  H01L21/67132 ,  H01L21/6835 ,  H01L21/6836 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68354 ,  H01L2224/11003 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/10253 ,  Y10S414/139 ,  H01L2924/00 ,  H01L2224/0401

摘要： A laser release and glass chip removal process for a integrated circuit module avoiding carrier edge cracking is provided.

摘要翻译： 提供了用于避免载波边缘破裂的集成电路模块的激光释放和玻璃切屑去除工艺。

公开(公告)号：US20070222065A1

公开(公告)日：2007-09-27

申请号：US11385121

申请日：2006-03-21

申请人： Paul Andry ,  Leena Buchwalter ,  Raymond Horton ,  John Knickerbocker ,  Cornelia Tsang ,  Steven Wright

发明人： Paul Andry ,  Leena Buchwalter ,  Raymond Horton ,  John Knickerbocker ,  Cornelia Tsang ,  Steven Wright

IPC分类号： H01L21/00 ,  H01L23/34

CPC分类号： H01L24/81 ,  H01L23/544 ,  H01L24/48 ,  H01L24/97 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/48227 ,  H01L2224/81001 ,  H01L2224/81054 ,  H01L2224/81136 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15157 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/20109 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An electronic dive and method of fabricating an electronic device. The method including placing a placement guide over a top surface of a module substrate, the placement guide having a guide opening, the guide opening extending from a top surface of the placement guide to a bottom surface of the placement guide; aligning the placement guide to an integrated circuit chip position on the module substrate; fixing the placement guide to the module substrate; placing an integrated circuit chip in the guide opening, sidewalls of the placement guide opening constraining electrically conductive bonding structures on bottom surface of the integrated circuit chip to self-align to an electrically conductive module substrate contact pad on the top surface of the module substrate in the integrated circuit chip position; and bonding the bonding structures to the module substrate contact pads, the bonding structures and the module substrate contact pads in direct physical and electrical contact after the bonding.

摘要翻译： 一种电子潜水及其制造方法。 所述方法包括将放置引导件放置在模块基板的顶表面上，所述放置引导件具有引导开口，所述引导开口从所述放置引导件的顶表面延伸到所述放置引导件的底表面; 将所述放置引导件对准所述模块基板上的集成电路芯片位置; 将所述放置引导件固定到所述模块基板; 将集成电路芯片放置在引导开口中，放置引导开口的侧壁约束集成电路芯片的底表面上的导电接合结构，以与模块基板的顶表面上的导电模块衬底接触焊盘自对准 集成电路芯片位置; 以及在接合之后将结合结构粘合到模块衬底接触焊盘，接合结构和模块衬底接触焊盘，直接物理和电接触。

公开(公告)号：US20060177568A1

公开(公告)日：2006-08-10

申请号：US11049846

申请日：2005-02-04

申请人： Gareth Hougham ,  Leena Buchwalter ,  Stephen Buchwalter ,  Jon Casey ,  Claudius Feger ,  Matteo Flotta ,  Jeffrey Gelorme ,  Kathleen Hinge ,  Anurag Jain ,  Sung Kang ,  John Knickerbocker

发明人： Gareth Hougham ,  Leena Buchwalter ,  Stephen Buchwalter ,  Jon Casey ,  Claudius Feger ,  Matteo Flotta ,  Jeffrey Gelorme ,  Kathleen Hinge ,  Anurag Jain ,  Sung Kang ,  John Knickerbocker

IPC分类号： B05D5/12 ,  H05K3/00 ,  B05C1/00

CPC分类号： H05K3/4053 ,  B05D1/002 ,  H01L21/486 ,  H01L21/76898 ,  H05K2201/09509 ,  H05K2203/1554

摘要： The present disclosure relates generally to semiconductor, integrated circuits, and particularly, but not by way of limitation, to centrifugal methods of filling high-aspect ratio vias and trenches with powders, pastes, suspensions of materials to act as any of a conducting, structural support, or protective member of an electronic component.

摘要翻译： 本公开一般涉及半导体，集成电路，特别是但不限于，用于填充高纵横比通孔和沟槽的离心方法，其具有粉末，糊料，材料悬浮液，用作导电，结构 支撑或电子部件的保护构件。

公开(公告)号：US20060255480A1

公开(公告)日：2006-11-16

申请号：US10908480

申请日：2005-05-13

申请人： Jon Casey ,  Michael Berger ,  Leena Buchwalter ,  Donald Canaperi ,  Raymond Horton ,  Anurag Jain ,  Eric Perfecto ,  James Tornello

发明人： Jon Casey ,  Michael Berger ,  Leena Buchwalter ,  Donald Canaperi ,  Raymond Horton ,  Anurag Jain ,  Eric Perfecto ,  James Tornello

IPC分类号： H01L23/29

CPC分类号： H01L23/147 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/00

摘要： Sealing a via using a soventless, low viscosity, high temperature stable polymer or a high solids content polymer solution of low viscosity, where the polymeric material is impregnated within the via at an elevated temperature. A supply chamber is introduced to administer the polymeric material at an elevated temperature, typically at a temperature high enough to liquefy the polymeric material. The polymeric material is introduced through heated supply lines under force from a pump, piston, or a vacuum held within said supply chamber.

摘要翻译： 使用无粘性，低粘度，高温稳定的聚合物或低粘度的高固含量聚合物溶液密封通孔，其中聚合物材料在高温下浸渍在通孔内。 引入供应室以在升高的温度下施用聚合物材料，通常在高至足以液化聚合物材料的温度下。 聚合物材料通过来自泵，活塞或保持在所述供应室内的真空的力的加热供应管线引入。

公开(公告)号：US20080029889A1

公开(公告)日：2008-02-07

申请号：US11872229

申请日：2007-10-15

申请人： Leena Buchwalter ,  Russell Budd ,  Chirag Patel

发明人： Leena Buchwalter ,  Russell Budd ,  Chirag Patel

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L21/4853 ,  G01R1/0408 ,  G01R1/06716 ,  G01R1/07307 ,  H01L23/49811 ,  H01L23/562 ,  H01L24/81 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00

摘要： A method of producing flexible interconnections for integrated circuits, and, in particular, the forming of flexible or compliant interconnections preferably by a laser-assisted chemical vapor deposition process in semiconductor or glass substrate-based carriers which are employed for mounting and packaging multiple integrated circuit chips and selectively, other devices in the technology.

摘要翻译： 一种制造用于集成电路的柔性互连的方法，特别地，优选地通过半导体或基于玻璃衬底的载体中的激光辅助化学气相沉积工艺形成柔性或柔性互连件，所述方法用于安装和封装多个集成电路 芯片和选择性，其他设备的技术。

公开(公告)号：US20060186540A1

公开(公告)日：2006-08-24

申请号：US11063449

申请日：2005-02-23

申请人： Leena Buchwalter ,  Russell Budd ,  Chirag Patel

发明人： Leena Buchwalter ,  Russell Budd ,  Chirag Patel

IPC分类号： H01L23/48

CPC分类号： H01L21/4853 ,  G01R1/0408 ,  G01R1/06716 ,  G01R1/07307 ,  H01L23/49811 ,  H01L23/562 ,  H01L24/81 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00

摘要： A method of producing flexible interconnections for integrated circuits, and, in particular, the forming of flexible or compliant interconnections preferably by a laser-assisted chemical vapor deposition process in semiconductor or glass substrate-based carriers which are employed for mounting and packaging multiple integrated circuit chips and selectively, other devices in the technology.

摘要翻译： 一种制造用于集成电路的柔性互连的方法，特别地，优选地通过半导体或基于玻璃衬底的载体中的激光辅助化学气相沉积工艺形成柔性或柔性互连件，所述方法用于安装和封装多个集成电路 芯片和选择性，其他设备的技术。

公开(公告)号：US20050082676A1

公开(公告)日：2005-04-21

申请号：US10686640

申请日：2003-10-17

申请人： Paul Andry ,  Leena Buchwalter ,  Russell Budd ,  Thomas Wassick

发明人： Paul Andry ,  Leena Buchwalter ,  Russell Budd ,  Thomas Wassick

IPC分类号： H01L21/768 ,  H01L23/48

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： This disclosure teaches a method of filling deep vias or capping deep conducting paste filled vias in silicon or glass substrate using laser assisted chemical vapor deposition of metals. This method uses a continuous wave or pulsed laser to heat the via bottom and the growing metal fill selectively by selecting the laser wavelength such that silicon and/or glass do not absorb the energy of the laser in any appreciable manner to cause deposition in the field. Alternatively holographic mask or an array of micro lenses may be used to focus the laser beams to the vias to fill them with metal. The substrate is moved in a controlled manner in the z-direction away from the laser at about the rate of deposition thus causing the laser heating to be focused on the surface region of the growing metal fill.

摘要翻译： 该公开内容教导了使用金属的激光辅助化学气相沉积在硅或玻璃基板中填充深通孔或者封装深导电糊填充通孔的方法。 该方法使用连续波或脉冲激光器通过选择激光波长来选择性地加热通孔底部和生长金属填充物，使得硅和/或玻璃不以任何可察觉的方式吸收激光的能量以在场中沉积 。 或者，可以使用全息掩模或微透镜阵列来将激光束聚焦到通孔以用金属填充它们。 以大约的沉积速率，以z方向以受控方式远离激光器移动衬底，从而使激光加热聚焦在生长金属填充物的表面区域上。

公开(公告)号：US20050168947A1

公开(公告)日：2005-08-04

申请号：US10733672

申请日：2003-12-11

申请人： Lawrence Mok ,  Leena Buchwalter ,  Stephen Buchwalter

发明人： Lawrence Mok ,  Leena Buchwalter ,  Stephen Buchwalter

IPC分类号： H01L23/427 ,  H01L23/473 ,  H02B1/00 ,  H05K7/20

CPC分类号： H01L23/427 ,  H01L23/473 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2924/10158 ,  H01L2924/00014

摘要： The invention is directed to structure and methods of improving the cooling capacity of chip packaging modules. The chip packaging module has a substrate with thin-film wiring on one side and grooves or channels etched on one or both sides where coolant pumps are embedded. The coolant pumps are used to enhance the liquid flowing inside the module. The coolant flows through the chips within the vias in the chips or around the chips when the chips do not have vias. Both cooling modes, single or two-phase modes can be adopted in the module.

摘要翻译： 本发明涉及提高芯片封装模块的冷却能力的结构和方法。 芯片封装模块具有在一侧具有薄膜布线的基板，在嵌入有冷却剂泵的一侧或两侧蚀刻的凹槽或通道。 冷却液泵用于增强模块内流动的液体。 当芯片没有通孔时，冷却剂流过芯片内或芯片周围的通孔内的芯片。 模块中可以采用两种冷却模式，单相或双相模式。