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1.发明申请Silicon chip carrier with conductive through-vias and method for fabricating same 有权具有导电通孔的硅芯片载体及其制造方法公开(公告)号：US20050121768A1
公开(公告)日：2005-06-09
申请号：US10729254
申请日：2003-12-05
申请人： Daniel Edelstein , Paul Andry , Leena Buchwalter , Jon Casey , Sherif Goma , Raymond Horton , Gareth Hougham , Michael Lane , Xiao Liu , Chirag Patel , Edmund Sprogis , Michelle Steen , Brian Sundlof , Cornelia Tsang , George Walker
发明人： Daniel Edelstein , Paul Andry , Leena Buchwalter , Jon Casey , Sherif Goma , Raymond Horton , Gareth Hougham , Michael Lane , Xiao Liu , Chirag Patel , Edmund Sprogis , Michelle Steen , Brian Sundlof , Cornelia Tsang , George Walker
IPC分类号： H01L21/48 , H01L21/768 , H01L23/498 , H01L23/48 , H01L21/4763
CPC分类号： H01L23/49883 , H01L21/486 , H01L21/76898 , H01L23/49827 , H01L2224/16 , H01L2924/01004 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/09701 , H01L2924/10253 , H01L2924/15311 , H01L2924/3011 , H01L2924/3025 , H01L2924/00
摘要： A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.
摘要翻译： 一种载体结构和方法，用于制造具有通孔的载流子结构，每个导通孔具有导电结构，其有效热膨胀系数小于或接近于基板的热膨胀系数，并且具有小于或等于 或者与衬底的密切匹配。 导电结构可以包括同心的通孔填充区域，其具有同心设置的不同材料，由导电材料的环形环包围的衬底材料的芯，由导电材料的环形环包围的CTE匹配的非导电材料的芯， 具有低CTE的内部空隙的导电通孔，或已经烧结或熔合的诸如金属 - 陶瓷浆料的导电复合材料的完整填充物。
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2.发明申请Silicon chip carrier with conductive through-vias and method for fabricating same 审中-公开具有导电通孔的硅芯片载体及其制造方法公开(公告)号：US20060027934A1
公开(公告)日：2006-02-09
申请号：US11242221
申请日：2005-10-03
申请人： Daniel Edelstein , Paul Andry , Leena Buchwalter , Jon Casey , Sherif Goma , Raymond Horton , Gareth Hougham , Michael Lane , Xiao Liu , Chirag Patel , Edmund Sprogis , Michelle Steen , Brian Sundlof , Cornelia Tsang , George Walker , Yu-Ting Cheng , Kenneth Ocheltree , Robert Montoye
发明人： Daniel Edelstein , Paul Andry , Leena Buchwalter , Jon Casey , Sherif Goma , Raymond Horton , Gareth Hougham , Michael Lane , Xiao Liu , Chirag Patel , Edmund Sprogis , Michelle Steen , Brian Sundlof , Cornelia Tsang , George Walker , Yu-Ting Cheng , Kenneth Ocheltree , Robert Montoye
IPC分类号： H01L23/48
CPC分类号： H01L23/49883 , H01L21/486 , H01L21/76898 , H01L23/49827 , H01L2224/16 , H01L2924/01004 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/09701 , H01L2924/10253 , H01L2924/15311 , H01L2924/3011 , H01L2924/3025 , H01L2924/00
摘要： A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.
摘要翻译： 一种载体结构和方法，用于制造具有通孔的载流子结构，每个导通孔具有导电结构，其有效热膨胀系数小于或接近于基板的热膨胀系数，并且具有小于或等于 或者与衬底的密切匹配。 导电结构可以包括同心的通孔填充区域，其具有同心设置的不同材料，由导电材料的环形环包围的衬底材料的芯，由导电材料的环形环包围的CTE匹配的非导电材料的芯， 具有低CTE的内部空隙的导电通孔，或已经烧结或熔合的诸如金属 - 陶瓷浆料的导电复合材料的完整填充物。
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公开(公告)号：US20070222065A1
公开(公告)日：2007-09-27
申请号：US11385121
申请日：2006-03-21
申请人： Paul Andry , Leena Buchwalter , Raymond Horton , John Knickerbocker , Cornelia Tsang , Steven Wright
发明人： Paul Andry , Leena Buchwalter , Raymond Horton , John Knickerbocker , Cornelia Tsang , Steven Wright
CPC分类号： H01L24/81 , H01L23/544 , H01L24/48 , H01L24/97 , H01L25/50 , H01L2223/54426 , H01L2223/54473 , H01L2224/05568 , H01L2224/05573 , H01L2224/05644 , H01L2224/05647 , H01L2224/13144 , H01L2224/13147 , H01L2224/16 , H01L2224/48227 , H01L2224/81001 , H01L2224/81054 , H01L2224/81136 , H01L2224/81203 , H01L2224/8121 , H01L2224/81815 , H01L2224/85444 , H01L2224/85447 , H01L2224/97 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/15157 , H01L2924/1517 , H01L2924/15174 , H01L2924/20109 , H01L2224/81 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An electronic dive and method of fabricating an electronic device. The method including placing a placement guide over a top surface of a module substrate, the placement guide having a guide opening, the guide opening extending from a top surface of the placement guide to a bottom surface of the placement guide; aligning the placement guide to an integrated circuit chip position on the module substrate; fixing the placement guide to the module substrate; placing an integrated circuit chip in the guide opening, sidewalls of the placement guide opening constraining electrically conductive bonding structures on bottom surface of the integrated circuit chip to self-align to an electrically conductive module substrate contact pad on the top surface of the module substrate in the integrated circuit chip position; and bonding the bonding structures to the module substrate contact pads, the bonding structures and the module substrate contact pads in direct physical and electrical contact after the bonding.
摘要翻译： 一种电子潜水及其制造方法。 所述方法包括将放置引导件放置在模块基板的顶表面上，所述放置引导件具有引导开口，所述引导开口从所述放置引导件的顶表面延伸到所述放置引导件的底表面; 将所述放置引导件对准所述模块基板上的集成电路芯片位置; 将所述放置引导件固定到所述模块基板; 将集成电路芯片放置在引导开口中，放置引导开口的侧壁约束集成电路芯片的底表面上的导电接合结构，以与模块基板的顶表面上的导电模块衬底接触焊盘自对准 集成电路芯片位置; 以及在接合之后将结合结构粘合到模块衬底接触焊盘，接合结构和模块衬底接触焊盘，直接物理和电接触。
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4.发明申请公开(公告)号：US20070048896A1
公开(公告)日：2007-03-01
申请号：US11214602
申请日：2005-08-30
申请人： Paul Andry , Chirag Patel , Edmund Sprogis , Cornelia Tsang
发明人： Paul Andry , Chirag Patel , Edmund Sprogis , Cornelia Tsang
IPC分类号： H01L21/00
CPC分类号： H01L23/49833 , H01L21/4853 , H01L21/486 , H01L21/6835 , H01L21/76898 , H01L23/481 , H01L23/49816 , H01L23/49827 , H01L2221/68345 , H01L2224/0401 , H01L2224/05567 , H01L2224/13009 , H01L2224/13022 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/81191 , H01L2924/0002 , H01L2924/09701 , H01L2924/12044 , H01L2924/3011 , Y10T29/49165 , H01L2924/014 , H01L2224/05552
摘要： Conductive through vias are formed in electronic devices and electronic device carrier, such as, a silicon chip carrier. An annulus cavity is etched into the silicon carrier from the top side of the carrier and the cavity is filled with insulating material to form an isolation collar around a silicon core region. An insulating layer with at least one wiring level, having a portion in contact with the silicon core region, is formed on the top side of the carrier. Silicon is removed from the back side of the carrier sufficient to expose the distal portion of the isolation collar. The core region is etched out to expose the portion of the wiring level in contact with the silicon core region to form an empty via. The via is filled with conductive material in contact with the exposed portion of the wiring level to form a conductive through via to the wiring level. A solder bump formed, for example, from low melt C4 solder, is formed on the conductive via exposed on the carrier back side. The process acts to make the conductive via fill step independent of the via isolation step.
摘要翻译： 导电通孔形成在电子器件和电子器件载体中，例如硅芯片载体。 环状空腔从载体的顶侧蚀刻到硅载体中，并且空腔填充绝缘材料以在硅芯区域周围形成隔离环。 在载体的顶侧上形成具有至少一个布线层的绝缘层，其具有与硅芯区域接触的部分。 将硅从载体的背面移除，足以露出隔离套环的远端部分。 蚀刻芯区域以暴露与硅芯区域接触的布线层的部分以形成空通孔。 通孔填充有与布线层的暴露部分接触的导电材料，以形成导电通孔到布线层。 在载体背侧露出的导电通孔上形成例如由低熔点C4焊料形成的焊料凸块。 该过程用于使导电通孔填充步骤独立于通孔隔离步骤。
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公开(公告)号：US20070035030A1
公开(公告)日：2007-02-15
申请号：US11201572
申请日：2005-08-11
IPC分类号： H01L23/48
CPC分类号： H01L23/49827 , H01L23/49822 , H01L23/50 , H01L23/5382 , H01L2224/16225 , H01L2224/16235 , H01L2924/01012 , H01L2924/01019 , H01L2924/0102 , H01L2924/01077 , H01L2924/01078 , H01L2924/15311
摘要： Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.
摘要翻译： 提供电子器件制造技术。 一方面，提供一种电子设备。 电子设备包括具有一个或多个通孔和集成在其中的多个去耦电容器的至少一个插入器结构，所述至少一个插入器结构被配置为允许选择性地去激活多个去耦电容器中的一个或多个。 在另一方面，一种制造电子器件的方法，包括至少一个具有一个或多个通孔的内插器结构和集成在其中的多个去耦电容器，其包括以下步骤。 选择性地去激活多个去耦电容器中的一个或多个。
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公开(公告)号：US20080067628A1
公开(公告)日：2008-03-20
申请号：US11930698
申请日：2007-10-31
IPC分类号： H01L29/00
CPC分类号： H01L23/49827 , H01L23/49822 , H01L23/50 , H01L23/5382 , H01L2224/16225 , H01L2224/16235 , H01L2924/01012 , H01L2924/01019 , H01L2924/0102 , H01L2924/01077 , H01L2924/01078 , H01L2924/15311
摘要： Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or mote vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated
摘要翻译： 提供电子器件制造技术。 一方面，提供一种电子设备。 该电子设备包括具有一个或多个微通孔和集成在其中的多个去耦电容器的至少一个插入器结构，所述至少一个插入器结构被配置为允许选择性地去激活多个去耦电容器中的一个或多个。 在另一方面，一种制造电子器件的方法，包括至少一个具有一个或多个通孔的内插器结构和集成在其中的多个去耦电容器，其包括以下步骤。 选择性地去激活多个去耦电容器中的一个或多个
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公开(公告)号：US20050037608A1
公开(公告)日：2005-02-17
申请号：US10639989
申请日：2003-08-13
申请人： Panayotis Andricacos , Emanuel Cooper , Timothy Dalton , Hariklia Deligianni , Daniel Guidotti , Keith Kwietniak , Michelle Steen , Cornelia Tsang
发明人： Panayotis Andricacos , Emanuel Cooper , Timothy Dalton , Hariklia Deligianni , Daniel Guidotti , Keith Kwietniak , Michelle Steen , Cornelia Tsang
IPC分类号： H01L21/288 , H01L21/3065 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/2885 , H01L21/30655 , H01L21/76898
摘要： Flared and non-flared metallized deep vias having aspect ratios of about 2 or greater are provided. Blind vias have been fabricated in silicon substrates up to a depth of about 300 microns, and flared through vias have been fabricated up to about 750 microns, the approximate thickness of a silicon substrate wafer, enabling the formation of electrical connections at either or both ends of a via. In spite of the depth and high aspect ratios attainable, the etched vias are completely filled with plated copper conductor, completing the formation of deep vias and allowing fuller use of both sides of the substrate.
摘要翻译： 提供具有约2或更大的纵横比的扩张和未扩口的金属化深通孔。 盲孔已经在硅衬底中制造达到约300微米的深度，并且通过通孔已经被制造高达约750微米，硅衬底晶片的大致厚度，使得能够在两端或两端形成电连接 的通道。 尽管可以获得深度和高纵横比，但是蚀刻的通孔完全被电镀铜导体填充，从而形成深通孔并允许更充分地使用基板的两侧。
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公开(公告)号：US20110199108A1
公开(公告)日：2011-08-18
申请号：US13095969
申请日：2011-04-28
IPC分类号： G01R31/20
CPC分类号： G01R3/00 , G01R1/07378
摘要： A silicon chicklet pedestal for use in a wafer-level test probe of a wafer is provided and includes a main body, first and second opposing faces, and an array of vias formed through the main body to extend between the first and second faces, through which pairs of leads, respectively associated with each via at the first and second faces, are electrically connectable to one another.
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公开(公告)号：US20110199109A1
公开(公告)日：2011-08-18
申请号：US13095973
申请日：2011-04-28
CPC分类号： G01R3/00 , G01R1/07378
摘要： A silicon chicklet pedestal for use in a wafer-level test probe of a wafer is provided and includes a main body, first and second opposing faces, and an array of vias formed through the main body to extend between the first and second faces, through which pairs of leads, respectively associated with each via at the first and second faces, are electrically connectable to one another.
摘要翻译： 提供了一种用于晶片的晶片级测试探针中的硅芯座，包括主体，第一和第二相对面以及通过主体形成的通孔阵列，以在第一和第二面之间延伸通过 分别与第一和第二表面上的每个通孔相关联的引线对可彼此电连接。
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公开(公告)号：US20110037489A1
公开(公告)日：2011-02-17
申请号：US12540487
申请日：2009-08-13
CPC分类号： G01R3/00 , G01R1/07378
摘要： A silicon chicklet pedestal for use in a wafer-level test probe of a wafer is provided and includes a main body, first and second opposing faces, and an array of vias formed through the main body to extend between the first and second faces, through which pairs of leads, respectively associated with each via at the first and second faces, are electrically connectable to one another.
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