公开(公告)号：US6117785A

公开(公告)日：2000-09-12

申请号：US891360

申请日：1997-07-10

申请人： Hae-jeong Lee ,  Ji-hyun Choi ,  Byung-keun Hwang ,  Ju-seon Goo

发明人： Hae-jeong Lee ,  Ji-hyun Choi ,  Byung-keun Hwang ,  Ju-seon Goo

IPC分类号： H01L21/3213 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  H01L21/31

CPC分类号： H01L21/76804 ,  H01L21/31144

摘要： A method for forming a microelectronic device includes the steps of forming a spin-on-glass layer on a microelectronic substrate, and forming a capping layer on the spin-on-glass layer opposite the substrate. A masking layer is formed on the capping layer opposite the substrate wherein the masking layer exposes portions of the capping layer and the spin-on-glass layer. The exposed portions of said capping layer and the spin-on-glass layer are etched using the masking layer as an etch mask to thereby form a contact hole through the capping layer and the spin-on-glass layer wherein protruding edge portions of the capping layer extend beyond the spin-on-glass layer adjacent the contact hole. The mask layer is removed, and the protruding edge portions of the capping layer are removed from adjacent the contact hole.

摘要翻译： 一种形成微电子器件的方法包括以下步骤：在微电子衬底上形成旋涂玻璃层，并在与衬底相对的旋转玻璃层上形成覆盖层。 在与衬底相对的覆盖层上形成掩模层，其中掩模层露出覆盖层和旋涂玻璃层的部分。 使用掩模层作为蚀刻掩模蚀刻所述覆盖层和旋涂玻璃层的暴露部分，从而通过覆盖层和旋涂玻璃层形成接触孔，其中封盖的突出边缘部分 层延伸超过接触孔附近的旋涂玻璃层。 去除掩模层，并且覆盖层的突出边缘部分从邻近的接触孔去除。

公开(公告)号：US5989983A

公开(公告)日：1999-11-23

申请号：US921621

申请日：1997-08-27

申请人： Ju-seon Goo ,  Ji-hyun Choi ,  Byung-keun Hwang ,  Hae-jeong Lee

发明人： Ju-seon Goo ,  Ji-hyun Choi ,  Byung-keun Hwang ,  Hae-jeong Lee

IPC分类号： H01L21/3205 ,  H01L21/3105 ,  H01L21/312 ,  H01L21/316 ,  H01L21/768 ,  H01L21/322

CPC分类号： H01L21/02134 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/0234 ,  H01L21/02351 ,  H01L21/02362 ,  H01L21/3105 ,  H01L21/3124 ,  H01L21/316 ,  H01L21/76825 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76801

摘要： An insulating layer may be fabricated on a microelectronic substrate by spinning a layer of spin-on-glass (SOG) on a microelectronic substrate and curing the SOG layer by irradiating the SOG layer with an electronic beam. Irradiating may take place simultaneously with heating the substrate to a temperature below about 500.degree. C. An underlying and/or overlying capping layer may also be provided. Alternatively, rather than irradiating the SOG layer, an overlying capping layer may be irradiated.

摘要翻译： 可以通过在微电子衬底上旋转旋涂玻璃（SOG）层并通过用电子束照射SOG层固化SOG层来在微电子衬底上制造绝缘层。 可以在将基底加热到低于约500℃的温度的同时进行辐照。还可以提供下层和/或上覆盖层。 或者，不是照射SOG层，而是可以照射上覆盖层。

公开(公告)号：US6057251A

公开(公告)日：2000-05-02

申请号：US164938

申请日：1998-10-01

申请人： Ju-seon Goo ,  Seong-ho Kim ,  Hae-jeong Lee ,  Byung-keun Hwang

发明人： Ju-seon Goo ,  Seong-ho Kim ,  Hae-jeong Lee ,  Byung-keun Hwang

IPC分类号： H01L21/31 ,  H01L21/3105 ,  H01L21/312 ,  H01L21/316 ,  H01L21/768

CPC分类号： H01L21/02362 ,  H01L21/02129 ,  H01L21/02131 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02351 ,  H01L21/3105 ,  H01L21/31612 ,  H01L21/31625 ,  H01L21/31629 ,  H01L21/76825 ,  H01L21/76829 ,  H01L21/31053

摘要： A method for stabilizing an interlevel dielectric layer formed by a chemical vapor deposition (CVD) process, using electron beams. A CVD oxide layer is formed on a semiconductor substrate. The CVD oxide layer is radiated with electron beams at a temperature of between approximately room temperature and approximately 500.degree. C. for a predetermined time, using an electron beam radiator, to densify the layer.

摘要翻译： 一种使用电子束稳定化学气相沉积（CVD）工艺形成的层间电介质层的方法。 在半导体衬底上形成CVD氧化物层。 使用电子束辐射器在约室温至约500℃的温度下用电子束辐射CVD氧化物层以致密化层。

公开(公告)号：US08492223B2

公开(公告)日：2013-07-23

申请号：US13085631

申请日：2011-04-13

申请人： Jong-wan Choi ,  Wan-sik Hwang ,  Gil-heyun Choi ,  Eunkee Hong ,  Ju-seon Goo ,  Bo-young Lee

发明人： Jong-wan Choi ,  Wan-sik Hwang ,  Gil-heyun Choi ,  Eunkee Hong ,  Ju-seon Goo ,  Bo-young Lee

IPC分类号： H01L21/321

CPC分类号： H01L21/3105 ,  H01L21/76826 ,  H01L27/11521

摘要： A method of manufacturing a flash memory device includes: forming a dielectric layer on an active region of a substrate having an isolation region and the active region; forming a floating gate on the dielectric layer; forming an isolation layer in the isolation region; forming a nitride layer including a first nitride layer portion formed on an exposed surface of the floating gate and a second nitride layer portion formed on an exposed surface of the isolation layer; selectively removing nitrogen atoms from the second nitride layer portion of the nitride layer; forming an inter-gate dielectric layer on both the first nitride layer portion and the isolation layer; and forming a control gate on the inter-gate dielectric layer.

摘要翻译： 制造闪速存储器件的方法包括：在具有隔离区域和有源区域的衬底的有源区上形成电介质层; 在介电层上形成浮栅; 在隔离区中形成隔离层; 形成包括形成在所述浮置栅极的暴露表面上的第一氮化物层部分和形成在所述隔离层的暴露表面上的第二氮化物层部分的氮化物层; 从氮化物层的第二氮化物层部分选择性地除去氮原子; 在所述第一氮化物层部分和所述隔离层上形成栅极间电介质层; 以及在所述栅极间电介质层上形成控制栅极。

公开(公告)号：US20100167490A1

公开(公告)日：2010-07-01

申请号：US12629920

申请日：2009-12-03

申请人： Jong-wan Choi ,  Yong-soon Choi ,  Bo-young Lee ,  Eunkee Hong ,  Eun-kyung Baek ,  Ju-seon Goo

发明人： Jong-wan Choi ,  Yong-soon Choi ,  Bo-young Lee ,  Eunkee Hong ,  Eun-kyung Baek ,  Ju-seon Goo

IPC分类号： H01L21/762

CPC分类号： H01L27/11521 ,  H01L27/11524

摘要： Provided are methods of fabricating flash memory devices that may prevent a short circuit from occurring between cell gate lines. Methods of fabricating such flash memory devices may include forming gate lines including a series of multiple cell gate lines and multiple selection gate lines. Each gate line may include a stacked structure of a tunnel insulating layer, a floating gate, a gate insulating layer, and/or a polysilicon layer operable to be a control gate, all formed on a semiconductor substrate. Methods may include forming a first insulating layer that selectively fills gaps between the cell gate lines from the bottom up and between adjacent ones of the cell gate lines and the selection gate lines, and does not fill a space located on outer sides of the selection gate lines that are opposite the plurality of cell gate lines. A spacer may be formed on the outer sides of the selection gate lines that are opposite to the cell gate lines, after forming the first insulating layer. A second insulating layer may be formed in a space where the spacer is formed.

摘要翻译： 提供了制造闪存器件的方法，其可以防止在单元栅极线之间发生短路。 制造这种闪存器件的方法可以包括形成包括一系列多单元栅极线和多个选择栅极线的栅极线。 每个栅极线可以包括全部形成在半导体衬底上的隧道绝缘层，浮动栅极，栅极绝缘层和/或可操作为控制栅极的多晶硅层的堆叠结构。 方法可以包括形成第一绝缘层，其选择性地从底部向上和相邻的单元栅极线和选择栅极线之间填充单元栅极线之间的间隙，并且不填充位于选择栅极的外侧的空间 与多个单元栅极线相对的线。 在形成第一绝缘层之后，可以在选择栅极线的与单元栅极线相对的外侧上形成间隔物。 可以在形成间隔物的空间中形成第二绝缘层。

公开(公告)号：US06368906B1

公开(公告)日：2002-04-09

申请号：US09209317

申请日：1998-12-09

申请人： Hong-jae Shin ,  Ju-seon Goo

发明人： Hong-jae Shin ,  Ju-seon Goo

IPC分类号： H01L218242

CPC分类号： H01L21/3105 ,  H01L21/31056 ,  H01L21/31111 ,  H01L27/10808 ,  H01L27/10894

摘要： A method for planarizing an interlayer dielectric layer formed on a semiconductor substrate having a step, using wet etch, by depositing first and second layers on the semiconductor substrate and selectively curing the second layer in the lower area using electron beams (E-beams). The second layer, e.g., an SOG layer formed of HSQ, has a lower etch rate during the wet etch in the cured area, to thereby easily planarize the substrate of the interlayer dielectric layer.

摘要翻译： 一种使半导体衬底上形成的层间电介质层平坦化的方法，该层间绝缘层具有通过在半导体衬底上沉积第一层和第二层并使用电子束（E-beam）选择性地固化下部区域中的第二层的步骤。 第二层，例如由HSQ形成的SOG层在固化区域的湿蚀刻期间具有较低的蚀刻速率，从而容易地平坦化层间电介质层的衬底。

公开(公告)号：US08043914B2

公开(公告)日：2011-10-25

申请号：US12629920

申请日：2009-12-03

申请人： Jong-wan Choi ,  Yong-soon Choi ,  Bo-young Lee ,  Eunkee Hong ,  Eun-kyung Baek ,  Ju-seon Goo

发明人： Jong-wan Choi ,  Yong-soon Choi ,  Bo-young Lee ,  Eunkee Hong ,  Eun-kyung Baek ,  Ju-seon Goo

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/11524

摘要： Provided are methods of fabricating flash memory devices that may prevent a short circuit from occurring between cell gate lines. Methods of fabricating such flash memory devices may include forming gate lines including a series of multiple cell gate lines and multiple selection gate lines. Each gate line may include a stacked structure of a tunnel insulating layer, a floating gate, a gate insulating layer, and/or a polysilicon layer operable to be a control gate, all formed on a semiconductor substrate. Methods may include forming a first insulating layer that selectively fills gaps between the cell gate lines from the bottom up and between adjacent ones of the cell gate lines and the selection gate lines, and does not fill a space located on outer sides of the selection gate lines that are opposite the plurality of cell gate lines. A spacer may be formed on the outer sides of the selection gate lines that are opposite to the cell gate lines, after forming the first insulating layer. A second insulating layer may be formed in a space where the spacer is formed.

摘要翻译： 提供了制造闪存器件的方法，其可以防止在单元栅极线之间发生短路。 制造这种闪存器件的方法可以包括形成包括一系列多单元栅极线和多个选择栅极线的栅极线。 每个栅极线可以包括全部形成在半导体衬底上的隧道绝缘层，浮动栅极，栅极绝缘层和/或可操作为控制栅极的多晶硅层的堆叠结构。 方法可以包括形成第一绝缘层，其选择性地从底部向上和相邻的单元栅极线和选择栅极线之间填充单元栅极线之间的间隙，并且不填充位于选择栅极的外侧的空间 与多个单元栅极线相对的线。 在形成第一绝缘层之后，可以在选择栅极线的与单元栅极线相对的外侧上形成间隔物。 可以在形成间隔物的空间中形成第二绝缘层。

公开(公告)号：US20110256708A1

公开(公告)日：2011-10-20

申请号：US13085631

申请日：2011-04-13

申请人： Jong-wan Choi ,  Wan-sik Hwang ,  Gil-heyun Choi ,  Eunkee Hong ,  Ju-seon Goo ,  Bo-young Lee

发明人： Jong-wan Choi ,  Wan-sik Hwang ,  Gil-heyun Choi ,  Eunkee Hong ,  Ju-seon Goo ,  Bo-young Lee

IPC分类号： H01L21/321 ,  H01L21/283

CPC分类号： H01L21/3105 ,  H01L21/76826 ,  H01L27/11521

摘要： A method of manufacturing a flash memory device includes: forming a dielectric layer on an active region of a substrate having an isolation region and the active region; forming a floating gate on the dielectric layer; forming an isolation layer in the isolation region; forming a nitride layer including a first nitride layer portion formed on an exposed surface of the floating gate and a second nitride layer portion formed on an exposed surface of the isolation layer; selectively removing nitrogen atoms from the second nitride layer portion of the nitride layer; forming an inter-gate dielectric layer on both the first nitride layer portion and the isolation layer; and forming a control gate on the inter-gate dielectric layer.

摘要翻译： 制造闪速存储器件的方法包括：在具有隔离区域和有源区域的衬底的有源区上形成电介质层; 在介电层上形成浮栅; 在隔离区中形成隔离层; 形成包括形成在所述浮置栅极的暴露表面上的第一氮化物层部分和形成在所述隔离层的暴露表面上的第二氮化物层部分的氮化物层; 从氮化物层的第二氮化物层部分选择性地除去氮原子; 在所述第一氮化物层部分和所述隔离层上形成栅极间电介质层; 以及在所述栅极间电介质层上形成控制栅极。

公开(公告)号：US20070117412A1

公开(公告)日：2007-05-24

申请号：US11656469

申请日：2007-01-23

申请人： Ju-seon Goo ,  Eun-kee Hong ,  Hong-Gun Kim ,  Kyu-tae Na

发明人： Ju-seon Goo ,  Eun-kee Hong ,  Hong-Gun Kim ,  Kyu-tae Na

IPC分类号： H01L21/31

CPC分类号： H01L21/02222 ,  H01L21/02164 ,  H01L21/02282 ,  H01L21/02326 ,  H01L21/02343 ,  H01L21/3125 ,  H01L21/3165 ,  H01L21/76229 ,  H01L21/76826 ,  H01L21/76828

摘要： A method is provided for forming silicon oxide layers during the processing of semiconductor devices by applying a SOG layer including polysilazane to a substrate and then substantially converting the SOG layer to a silicon oxide layer using an oxidant solution. The oxidant solution may include one or more oxidants including, for example, ozone, peroxides, permanganates, hypochlorites, chlorites, chlorates, perchlorates, hypobromites, bromites, bromates, hypoiodites, iodites, iodates and strong acids.

摘要翻译： 提供了一种通过将包含聚硅氮烷的SOG层施加到衬底然后使用氧化剂溶液将SOG层基本上转化为氧化硅层来在半导体器件加工期间形成氧化硅层的方法。 氧化剂溶液可以包括一种或多种氧化剂，包括例如臭氧，过氧化物，高锰酸盐，次氯酸盐，亚氯酸盐，氯酸盐，高氯酸盐，次溴酸盐，溴酸盐，溴酸盐，次碘酸盐，碘酸盐，碘酸盐和强酸。