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27 条记录 (耗时 0.029 秒)

    Semiconductor device and fabricating method thereof
    1.
    发明授权
    Semiconductor device and fabricating method thereof 有权
    半导体器件及其制造方法

    公开(公告)号：US09287270B2

    公开(公告)日：2016-03-15

    申请号：US14279301

    申请日：2014-05-15

    申请人： Jung-Hwan Oh ,  Hyun-Jun Kim ,  Jong-Bom Seo ,  Ki-Vin Im ,  Han-Jin Lim

    发明人： Jung-Hwan Oh ,  Hyun-Jun Kim ,  Jong-Bom Seo ,  Ki-Vin Im ,  Han-Jin Lim

    IPC分类号： H01L27/108 ,  H01L49/02

    CPC分类号： H01L27/10805 ,  H01L27/10808 ,  H01L27/1085 ,  H01L28/91

    摘要： Provided are a semiconductor device and a fabricating method thereof. The semiconductor device includes a storage electrode having a cylinder shape, a dielectric film formed on the storage electrode, and a plate electrode formed on the dielectric film, wherein the plate electrode includes a first semiconductor compound layer and a second semiconductor compound layer sequentially stacked one on the other, and the first semiconductor compound layer has a crystallinity different from that of the second semiconductor compound layer.

    摘要翻译： 提供一种半导体器件及其制造方法。 半导体器件包括具有圆柱形状的存储电极，形成在存储电极上的电介质膜和形成在电介质膜上的平板电极，其中该平板电极包括一个第一半导体化合物层和第二半导体化合物层， 另一方面，第一半导体化合物层的结晶度与第二半导体化合物层的结晶度不同。

    Method of oxidizing a silicon substrate and method of forming an oxide layer using the same
    4.
    发明授权
    Method of oxidizing a silicon substrate and method of forming an oxide layer using the same 有权
    氧化硅衬底的方法和使用其形成氧化物层的方法

    公开(公告)号：US07119029B2

    公开(公告)日：2006-10-10

    申请号：US10839501

    申请日：2004-05-05

    申请人： Won-Sik Shin ,  Ki-Hyun Hwang ,  Jung-Hwan Oh ,  Hyeon-Deok Lee ,  Seok-Woo Nam

    发明人： Won-Sik Shin ,  Ki-Hyun Hwang ,  Jung-Hwan Oh ,  Hyeon-Deok Lee ,  Seok-Woo Nam

    IPC分类号： H01L23/48

    CPC分类号： H01L21/02238 ,  C23C8/12 ,  C23C8/28 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/3144

    摘要： In a method of forming an oxide layer, ozone is generated by reacting an oxygen gas having a first flow rate with a nitrogen gas having a second flow rate of more than about 1% of the first flow rate. A reactant including the ozone and nitrogen is provided onto a silicon substrate. A surface of the silicon substrate is oxidized via the reaction of the reactant with silicon in the silicon substrate. The flow rate of the nitrogen gas is increased while ozone serving as an oxidant is formed by reacting the nitrogen gas with the oxygen gas. Thus, the oxide layer or a metal oxide layer including nitrogen may be rapidly formed on the substrate.

    摘要翻译： 在形成氧化物层的方法中，通过使具有第一流量的氧气与具有大于第一流量的约1％的第二流量的氮气反应来生成臭氧。 将包含臭氧和氮的反应物提供到硅衬底上。 硅衬底的表面通过反应物与硅衬底中的硅的反应被氧化。 通过使氮气与氧气反应而形成臭氧作为氧化剂，氮气的流量增加。 因此，可以在衬底上快速形成包含氮的氧化物层或金属氧化物层。

    One-cylinder stack capacitor and method for fabricating the same
    5.
    发明授权
    One-cylinder stack capacitor and method for fabricating the same 有权
    单缸电容器及其制造方法

    公开(公告)号：US06911364B2

    公开(公告)日：2005-06-28

    申请号：US10687838

    申请日：2003-10-20

    申请人： Jung-Hwan Oh ,  Ki-Hyun Hwang ,  Jae-Young Park ,  In-Seak Hwang ,  Young-Wook Park

    发明人： Jung-Hwan Oh ,  Ki-Hyun Hwang ,  Jae-Young Park ,  In-Seak Hwang ,  Young-Wook Park

    IPC分类号： H01L21/02 ,  H01L21/8242

    CPC分类号： H01L28/91 ,  H01L27/10855

    摘要： An etch stop layer is formed over a surface of an interlayer insulating layer and over a surface of a conductive plug extending at a depth from the surface of the interlayer insulating layer. A lower mold layer is deposited over the etch stop layer, and a wet etch rate of the lower mold layer is adjusted by adding dopants to the lower mold layer during formation of the lower mold layer, and by annealing the lower mold layer. An upper mold layer is then deposited over the surface of the lower mold layer, such that a wet etch rate of the upper mold layer is less than the adjusted wet etch rate of the lower mold layer. The upper mold layer, the lower mold layer and the etch stop layer are then subjected to dry etching to form an opening therein which exposes at least a portion of the surface of the contact plug. Then a wet etching of the upper mold layer and the lower mold layer is performed so as to increase a size of the opening at the lower mold layer and so at to expose a surface portion of the etch stop layer adjacent the surface of the conductive plug. A conductive material is then deposited over the surface of the opening in the upper and lower mold layers to define a capacitor electrode.

    摘要翻译： 在层间绝缘层的表面上方和在从层间绝缘层的表面的深度延伸的导电插塞的表面之上形成蚀刻停止层。 在蚀刻停止层上沉积下模层，并且通过在形成下模层期间向下模层添加掺杂剂并且通过对下模层进行退火来调节下模层的湿蚀刻速率。 然后将上模层沉积在下模层的表面上，使得上模层的湿蚀刻速率小于下模层的经调整的湿蚀刻速率。 然后对上模层，下模层和蚀刻停止层进行干蚀刻以在其中形成露出接触塞表面的至少一部分的开口。 然后进行上模层和下模层的湿式蚀刻，以便增加下模层上开口的尺寸，从而暴露出邻近导电塞表面的蚀刻停止层的表面部分 。 然后将导电材料沉积在上模具层和下模层中的开口的表面上，以限定电容器电极。

    Recessed gate electrode and method of forming the same and semiconductor device having the recessed gate electrode and method of manufacturing the same
    7.
    发明授权
    Recessed gate electrode and method of forming the same and semiconductor device having the recessed gate electrode and method of manufacturing the same 有权
    嵌入式栅电极及其形成方法以及具有凹陷栅电极的半导体器件及其制造方法

    公开(公告)号：US07563677B2

    公开(公告)日：2009-07-21

    申请号：US11531239

    申请日：2006-09-12

    申请人： Dae-Han Yoo ,  Kong-Soo Lee ,  Chang-Hoon Lee ,  Yong-Woo Hyung ,  Hyeon-Deok Lee ,  Hyo-Jung Kim ,  Jung-Hwan Oh ,  Young-Sub You

    发明人： Dae-Han Yoo ,  Kong-Soo Lee ,  Chang-Hoon Lee ,  Yong-Woo Hyung ,  Hyeon-Deok Lee ,  Hyo-Jung Kim ,  Jung-Hwan Oh ,  Young-Sub You

    IPC分类号： H01L21/336

    CPC分类号： H01L27/10894 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/66621

    摘要： A recessed gate electrode structure includes a first recess and a second recess in communication with the first recess both formed in a substrate. The second recess is larger than the first recess. A gate dielectric layer is formed on a top surface of the substrate and on an inner surface of the first and second recesses. A first polysilicon layer fills the first recess and is doped with impurities at a first impurity density. A second polysilicon layer fills the second recess and is doped with the impurities at a second impurity density. A void is defined within the second polysilicon layer. A third polysilicon layer is formed on the gate dielectric and first polysilicon layers and is doped with the impurities at a third impurity density. Due to impurities in the second polysilicon layer, migration of the void within the second recess may be substantially prevented.

    摘要翻译： 凹陷栅极电极结构包括第一凹部和与形成在基板中的第一凹部连通的第二凹部。 第二凹部比第一凹部大。 栅极电介质层形成在基板的顶表面上和第一凹槽和第二凹槽的内表面上。 第一多晶硅层填充第一凹槽并以第一杂质密度掺杂杂质。 第二多晶硅层填充第二凹槽，并以第二杂质密度掺杂杂质。 在第二多晶硅层内限定空隙。 在栅极电介质和第一多晶硅层上形成第三多晶硅层，并以第三杂质密度掺杂杂质。 由于第二多晶硅层中的杂质，可以基本上防止第二凹陷内的空隙的迁移。

    METHOD AND APPARATUS USING ON-SCREEN KEYBOARD AS INPUT UNIT
    8.
    发明申请
    METHOD AND APPARATUS USING ON-SCREEN KEYBOARD AS INPUT UNIT 有权
    使用屏幕键盘作为输入单元的方法和设备

    公开(公告)号：US20090044135A1

    公开(公告)日：2009-02-12

    申请号：US11969251

    申请日：2008-01-04

    申请人： Jung-Hwan Oh ,  Go-Un Lee ,  Sang-Chun Byun

    发明人： Jung-Hwan Oh ,  Go-Un Lee ,  Sang-Chun Byun

    IPC分类号： G06F3/048

    CPC分类号： G06F3/0236 ,  G06F3/04886

    摘要： A method and apparatus using an on-screen keyboard as an input unit. A method of using an on-screen keyboard as an input unit comprises receiving information on a first key that is selected through the input unit that has fewer input keys than the on-screen keyboard, highlighting a predetermined key in a predetermined group of keys including a number key on the on-screen keyboard that corresponds to the first key, and moving a highlighted portion on the on-screen keyboard when a second key is selected through the input unit.

    摘要翻译： 使用屏幕键盘作为输入单元的方法和装置。 一种使用屏幕上键盘作为输入单元的方法包括：通过输入单元选择的第一键上的信息具有比屏幕上键盘少的输入键，突出显示预定键组中的预定键，包括 对应于第一键的屏幕键盘上的数字键，以及当通过输入单元选择第二键时移动屏幕键盘上的高亮部分。

    CMOS IMAGE SENSORS AND METHODS OF FABRICATING SAME
    9.
    发明申请
    CMOS IMAGE SENSORS AND METHODS OF FABRICATING SAME 审中-公开
    CMOS图像传感器及其制造方法

    公开(公告)号：US20080296644A1

    公开(公告)日：2008-12-04

    申请号：US12187103

    申请日：2008-08-06

    申请人： Young-Sub You ,  Jung-Hwan Oh ,  Yong-Woo Hyung ,  Hun-Hyoung Lim

    发明人： Young-Sub You ,  Jung-Hwan Oh ,  Yong-Woo Hyung ,  Hun-Hyoung Lim

    IPC分类号： H01L27/146 ,  H01L21/28

    CPC分类号： H01L27/14623 ,  H01L27/14609 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14645 ,  H01L27/14685 ,  H01L27/14687 ,  H01L27/14689

    摘要： A CMOS image sensor includes an image transfer transistor therein. This image transfer transistor includes a semiconductor channel region of first conductivity type and an electrically conductive gate on the semiconductor channel region. A gate insulating region is also provided. The gate insulating region extends between the semiconductor channel region and the electrically conductive gate. The gate insulating region includes a nitridated insulating layer extending to an interface with the electrically conductive gate and a substantially nitrogen-free insulating layer extending to an interface with the semiconductor channel region. The nitridated insulating layer may be a silicon oxynitride (SiON) layer.

    摘要翻译： CMOS图像传感器包括其中的图像转移晶体管。 该图像传输晶体管包括半导体沟道区上的第一导电类型的半导体沟道区和导电栅。 还提供了栅极绝缘区域。 栅极绝缘区域在半导体沟道区域和导电栅极之间延伸。 栅极绝缘区域包括延伸到与导电栅极的界面的氮化绝缘层和延伸到与半导体沟道区域的界面的基本上无氮的绝缘层。 氮化绝缘层可以是氮氧化硅（SiON）层。

    Contact structure of semiconductor devices and method of fabricating the same
    10.
    发明授权
    Contact structure of semiconductor devices and method of fabricating the same 失效
    半导体器件的接触结构及其制造方法

    公开(公告)号：US08043960B2

    公开(公告)日：2011-10-25

    申请号：US11627139

    申请日：2007-01-25

    申请人： Jung-Hwan Oh ,  Byung-Lyul Park ,  Hong-Seong Son

    发明人： Jung-Hwan Oh ,  Byung-Lyul Park ,  Hong-Seong Son

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76879 ,  H01L21/288 ,  H01L21/76807 ,  H01L21/76814

    摘要： A contact structure includes a lower conductive pattern disposed on a predetermined region of a semiconductor substrate. The lower conductive layer has a concave region at a predetermined region of a top surface thereof. An embedding conductive layer fills the concave region. The top surface of the embedding conductive layer is placed at least as high as the height of the flat top surface of the lower conductive pattern. A mold layer is disposed to cover the semiconductor substrate, the lower conductive pattern and the embedding conductive layer. An upper conductive pattern is arranged in an intaglio pattern. The intaglio pattern is disposed in the mold layer to expose a predetermined region of the embedding conductive layer.

    摘要翻译： 接触结构包括设置在半导体衬底的预定区域上的下导电图案。 下导电层在其顶表面的预定区域具有凹区。 嵌入导电层填充凹区域。 嵌入导电层的顶表面至少与下导电图案的平坦顶表面的高度一样高。 模具层设置成覆盖半导体衬底，下导电图案和嵌入导电层。 上部导电图案以凹版图案布置。 凹版图案设置在模具层中以暴露嵌入导电层的预定区域。