公开(公告)号：US09826765B2

公开(公告)日：2017-11-28

申请号：US13728118

申请日：2012-12-27

申请人： Junya Kanayama ,  Hisashi Sugiyama ,  Masafumi Yamakoshi ,  Taku Ogura

发明人： Junya Kanayama ,  Hisashi Sugiyama ,  Masafumi Yamakoshi ,  Taku Ogura

IPC分类号： A23L1/16 ,  A23L1/162 ,  A23L7/113

CPC分类号： A23L7/113 ,  A23V2002/00

摘要： Provided is a dried noodle having a porosity in the cross-sectional area of the noodle of from 0.1 to 15%, a unit porosity in the cross-sectional area of the noodle of from 0.01 to 1%, a gelatinization degree of 30 to 75% and a porous structure.

公开(公告)号：US4918450A

公开(公告)日：1990-04-17

申请号：US367654

申请日：1989-06-19

申请人： Hisashi Sugiyama ,  Yasuhiro Sugimoto

发明人： Hisashi Sugiyama ,  Yasuhiro Sugimoto

IPC分类号： H03M1/36 ,  H03M1/12

CPC分类号： H03M1/1295 ,  H03M1/365

摘要： An analog/digital converter circuit including a capacitor having a first end, to which an analog voltage is applied, and a second end, an input buffer circuit having an input terminal, connected to the second end of said capacitor, and an output terminal, a reference voltage generating circuit for generating a plurality of reference voltages having different voltage levels, a voltage comparator circuit having a plurality of voltage comparators for comparing the output voltage of the input buffer circuit with each of the reference voltages generated by the reference voltage generating circuit, and generating a digital signal corresponding to the comparison results, a decoder circuit for decoding the output of the voltage comparator circuit, and D.C. bias voltage selection/supply circuit for selecting one of the reference voltages of the reference voltage generating circuit and supplying the selected reference voltage as a D.C. bias voltage to the input terminal of the input buffer circuit.

摘要翻译： 一种模拟/数字转换器电路，包括具有施加模拟电压的第一端和第二端的电容器，具有连接到所述电容器的第二端的输入端子的输入缓冲电路和输出端子， 用于产生具有不同电压电平的多个参考电压的参考电压产生电路，具有多个电压比较器的电压比较器电路，用于将输入缓冲器电路的输出电压与由参考电压产生电路产生的每个参考电压进行比较 并产生与比较结果相对应的数字信号，用于对电压比较器电路的输出进行解码的解码器电路以及用于选择参考电压发生电路的参考电压之一并提供所选择的电压的直流偏置电压选择/供给电路 参考电压作为直流偏置电压输入到输入缓冲器的输入端 它。

公开(公告)号：US5264319A

公开(公告)日：1993-11-23

申请号：US893946

申请日：1992-06-04

申请人： Hisashi Sugiyama ,  Kazuo Nate ,  Takashi Inoue ,  Akiko Mizushima

发明人： Hisashi Sugiyama ,  Kazuo Nate ,  Takashi Inoue ,  Akiko Mizushima

IPC分类号： C08G77/14 ,  C08G77/60 ,  C08K5/00 ,  G03F7/023 ,  G03F7/075

CPC分类号： G03F7/0757 ,  C08G77/14 ,  C08G77/60 ,  C08K5/0025 ,  G03F7/0233

摘要： Disclosed herein is a photosensitive resin composition composed mainly of an alkali-soluble organometallic polymer and a photosensitive dissolution inhibitor. The composition is used as a positive type resist which can be developed with an alkali developing solution. The resist has high sensitivity, high resolution, and resistance to oxygen plasma.

摘要翻译： 本文公开了主要由碱溶性有机金属聚合物和光敏溶解抑制剂组成的感光性树脂组合物。 该组合物用作可用碱性显影液显影的正型抗蚀剂。 抗蚀剂具有高灵敏度，高分辨率和耐氧等离子体。

公开(公告)号：US5034630A

公开(公告)日：1991-07-23

申请号：US476539

申请日：1990-02-07

申请人： Hisashi Sugiyama ,  Michinori Nakamura ,  Yasuhiro Sugimoto

发明人： Hisashi Sugiyama ,  Michinori Nakamura ,  Yasuhiro Sugimoto

IPC分类号： H03K19/086 ,  H03M7/00 ,  H03M7/14 ,  H03M7/16

CPC分类号： H03M7/14 ,  H03K19/0866 ,  H03M7/165

摘要： A logic circuit outputs state signals of seven different kinds, on the basis of first, second and third digital signals. A first composite gate circuit outputs a logical OR among the first to third digital signals as a first state signal. A first gate circuit outputs a logical OR between the second and third digital signals as a second state signal. A second composite gate circuit is supplied with a logical AND between the first and second digital signals, and outputs a logical OR between the supplied logical AND and the third digital signal as third state signal. A third composite gate circuit is supplied with a logical OR between the first and second digital signals, and outputs a logical AND between the supplied logical OR and the third digital signal as a fifth state signal. A second gate circuit outputs a logical AND between the second and third digital signals as a sixth state signal. A fourth composite gate circuit is supplied with a logical AND between the first and second digital signals, and outputs a logical AND between the supplied logical AND and the third digital signal as a seventh state signal. The third digital signal is output as a fourth state signal without being processed. Each of the above circuits has an emitter coupled logic structure.

公开(公告)号：US20120225448A1

公开(公告)日：2012-09-06

申请号：US13509338

申请日：2010-11-04

申请人： Hisashi Sugiyama ,  Satoshi Takahashi ,  Kenko Uchida ,  Satoshi Ozawa

发明人： Hisashi Sugiyama ,  Satoshi Takahashi ,  Kenko Uchida ,  Satoshi Ozawa

IPC分类号： C12Q1/02 ,  C12M1/34

CPC分类号： C12M47/04 ,  C12N1/02 ,  C12N11/02

摘要： When cells are analyzed, fractionated, and incubated while keeping the cells alive, real-time operations can be performed more easily and the cells can be incubated while removing unnecessary cells from the incubated cells to purify the cells being incubated. Furthermore, desired cells are separated through analysis from the incubated cells, and the purity, recovery, and viability of the cells are heightened. Use is made of a substrate having photo-controllable cell adhesion properties, the substrate comprising a transparent base and, formed thereon, a film of a material which has photo-controllable cell adhesion properties and has been obtained by bonding a cell-adhesive material to a cell-non-adhesive material through photo-dissociable groups. Cell images are detected and analyzed to obtain information about the location of desired cells. On the basis of the information, a space is formed between cells and the material having photo-controllable cell adhesion properties is cut, by means of second light irradiation. Meanwhile, by means of first light irradiation, the surface of the substrate is changed from a cell-adhesive surface to a cell-non-adhesive surface, thereby separating the cell(s) from the substrate. Thus, cells can be analyzed and fractionated while keeping the cells alive.

摘要翻译： 当细胞分析，分级和孵育同时保持细胞活着时，可以更容易地进行实时操作，并且可以孵育细胞，同时从培养的细胞中除去不需要的细胞以纯化待孵育的细胞。 此外，通过从培养的细胞的分析分离所需的细胞，并且提高细胞的纯度，回收率和存活力。 使用具有光可控细胞粘附性质的基材，所述基材包括透明基材，并且在其上形成具有光可控细胞粘附性的材料的膜，并且通过将细胞粘合剂材料粘合到 通过光解离基团的细胞非粘合材料。 检测和分析细胞图像以获得关于所需细胞位置的信息。 基于该信息，在单元之间形成空间，通过第二次光照射切断具有光可控细胞粘附性的材料。 同时，通过第一光照射，将基板的表面从电池 - 粘合剂表面改变为电池非粘合剂表面，从而将电池与基板分离。 因此，可以在保持细胞活着的同时分析和分级细胞。

公开(公告)号：US4798980A

公开(公告)日：1989-01-17

申请号：US49141

申请日：1987-05-13

申请人： Hisashi Sugiyama ,  Yasuhiro Sugimoto ,  Yukio Kamatani

发明人： Hisashi Sugiyama ,  Yasuhiro Sugimoto ,  Yukio Kamatani

IPC分类号： G06F7/53 ,  G06F7/44 ,  G06F7/52 ,  G06F7/533 ,  H03K19/21 ,  H03K19/017 ,  H03K19/094

CPC分类号： G06F7/5332

摘要： A Booth's algorithm conversion circuit having first and second switches controlled by input signals QX and Q2X and receiving as input, signals X.sub.i of a logic level positioned in the i digit order of a multiplicand X and signal X.sub.i-1 of a logic level positioned in the i-1 digit order of multiplicand X. The outputs of the first and second switches are tied together and to ground via first and second transitors controlled by signals QX and Q2X, the first and second transistors conducting in an inverse relationship to the first and second switch circuits. The common output of the first and second switch circuits is input to an exclusive OR circuit which receives an additional logic 1 or logic 0 input signal to produce the Booth's converted output. The resulting number of circuit elements and gates provides a simplified, high speed and small circuit for producing the Booth's conversion.

摘要翻译： 一种展位的算法转换电路，具有由输入信号QX和Q2X控制的第一和第二开关，并且接收位于被乘数X的i数位顺序的逻辑电平的信号Xi和位于该位置的逻辑电平的信号Xi-1 被乘数X的i-1位数。第一和第二开关的输出通过由信号QX和Q2X控制的第一和第二转换器连接在一起并接地，第一和第二晶体管与第一和第二开关反向关系 开关电路。 第一和第二开关电路的公共输出被输入到异或电路，该异或电路接收额外的逻辑1或逻辑0输入信号以产生布斯的转换输出。 所产生的电路元件和门的数量提供了简化的高速和小电路，用于生产Booth的转换。

公开(公告)号：US5539223A

公开(公告)日：1996-07-23

申请号：US36838

申请日：1993-03-25

申请人： Takeshi Sugoh ,  Hisashi Sugiyama

发明人： Takeshi Sugoh ,  Hisashi Sugiyama

IPC分类号： H01L21/82 ,  H01L21/822 ,  H01L23/528 ,  H01L27/04 ,  H01L27/118

CPC分类号： H01L27/11898 ,  H01L23/5286 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2924/14

摘要： A semicustom integrated circuit comprises pads arranged on peripheral portions of a chip along the four sides thereof. Peripheral circuit cells are arranged on a part of the chip to the inside of the pads. An internal circuit is arranged on a part of the chip to the inside of the peripheral circuit cell. The peripheral circuit cells include an ECL level input circuit an ECL level output circuit, a TTL level input circuit and a TTL level output circuit. Main source lines are formed on the peripheral circuit cells so as to surround the internal circuit. The main source lines are connected to pads to which source potentials is applied. Branch source lines cross the main source lines and connected to a selected one of the peripheral circuit cells and said internal circuit. The main source lines are selectively connected to the branch source lines by an interlayer connecting source line.

摘要翻译： 半定制集成电路包括沿其四边布置在芯片的周边部分上的焊盘。 外围电路单元布置在芯片的一部分上至衬垫的内部。 内部电路布置在芯片的一部分到外围电路单元的内部。 外围电路单元包括ECL电平输入电路，ECL电平输出电路，TTL电平输入电路和TTL电平输出电路。 主源极线形成在外围电路单元上，以便围绕内部电路。 主源极线连接到施加源电位的焊盘。 分支源极线穿过主要源极线并连接到所选择的外围电路单元和所述内部电路中的一个。 主源极线通过层间连接源极线选择性地连接到分支源极线。

公开(公告)号：US5480048A

公开(公告)日：1996-01-02

申请号：US113983

申请日：1993-08-30

申请人： Naoya Kitamura ,  Hisashi Sugiyama ,  Yoshihide Yamaguchi ,  Masayuki Kyoui ,  Hideyasu Murooka ,  Ryoji Iwamura ,  Makio Watanabe

发明人： Naoya Kitamura ,  Hisashi Sugiyama ,  Yoshihide Yamaguchi ,  Masayuki Kyoui ,  Hideyasu Murooka ,  Ryoji Iwamura ,  Makio Watanabe

IPC分类号： H01L21/48 ,  H05K3/10 ,  H05K3/24 ,  H05K3/42 ,  H05K3/46 ,  B44C1/22 ,  B29C37/00

CPC分类号： H01L21/4857 ,  H05K3/4647 ,  H05K2203/066 ,  H05K2203/0733 ,  H05K2203/1189 ,  H05K3/108 ,  H05K3/243 ,  H05K3/427 ,  H05K3/4602

摘要： A multilayer wiring board fabricating method and a multilayer wiring board fabricated with use of the method that a solvent-free fluid polymer precursor is put on a wiring layer of a base substrate, and space among the wirings is exhausted and is filled with the precursor, and the precursor is hardened under a hydrostatic pressure and then the next wiring layer is formed before the above process is repeated one or more times. The multilayer wiring board fabricating method is excellent in the mass productivity and low cost and in that the wiring can be made highly dense with the substrate having vertical via conductors for connection among the conductor layers.

摘要翻译： 使用将无溶剂的流体聚合物前体放在基底基板的布线层上的方法制造的多层布线板制造方法和多层布线板，并且布线之间的空间被排出并填充有前体， 并且在静水压力下将前体硬化，然后在上述过程重复一次或多次之前形成下一个布线层。 多层布线板的制造方法在质量生产率和低成本方面都是优异的，并且通过具有用于连接导体层之间的垂直通孔导体的基板，可以使布线高密度化。

公开(公告)号：US5158855A

公开(公告)日：1992-10-27

申请号：US247882

申请日：1988-09-22

申请人： Hisashi Sugiyama ,  Kazuo Nate ,  Akiko Mizushima ,  Keisuke Ebata

发明人： Hisashi Sugiyama ,  Kazuo Nate ,  Akiko Mizushima ,  Keisuke Ebata

IPC分类号： G03F7/016 ,  G03F7/023 ,  G03F7/075 ,  G03F7/36

CPC分类号： G03F7/0163

摘要： An .alpha.-diazoacetoacetic acid ester derived from cholic acid, deoxycholic acid, lithocholic acid or a derivative thereof is effective as a sensitizer in a photosensitive resin composition containing an alkali-soluble resin to form a resist for lithography using KrF excimer laser.

摘要翻译： 衍生自胆酸，脱氧胆酸，石胆酸或其衍生物的α-脱氮乙酰乙酸酯在含有碱溶性树脂的感光性树脂组合物中作为敏化剂是有效的，以形成使用KrF准分子激光的光刻抗蚀剂。

公开(公告)号：US4779016A

公开(公告)日：1988-10-18

申请号：US849

申请日：1987-01-06

申请人： Hisashi Sugiyama ,  Yasuhiro Sugimoto

发明人： Hisashi Sugiyama ,  Yasuhiro Sugimoto

IPC分类号： H03K19/0175 ,  H03K19/018 ,  H03K19/0944 ,  H03K19/092 ,  H03K19/094

CPC分类号： H03K19/09448 ,  H03K19/017527

摘要： Level conversion circuit for converting ECL logic level signals to CMOS logic level signals. The level conversion circuit includes: a differential amplifier circuit, which has a bipolar transistor of which the base terminal is connected to an input terminal and a bipolar transistor of which the base terminal is connected to a bias source, and which selects a current path from a high voltage source to a low voltage source; an MOS type transistor whose conduction is controlled by current flowing through the collector terminal of one of said bipolar transistors; a P-channel MOS type transistor, connected between the high voltage source and an output terminal, whose conduction is controlled either by the collector terminal current flowing through the collector terminal of the other of said bipolar transistors or by the drain terminal current flowing between the source termial and the drain terminal of said MOS transistor; and an N-channel MOS type transitor, connected between the low voltage source and the output terminal, whose conduction is controlled either said collector terminal current or by said drain terminal current.

摘要翻译： 电平转换电路，用于将ECL逻辑电平信号转换为CMOS逻辑电平信号。 电平转换电路包括：差分放大器电路，其具有基极端子连接到输入端子的双极晶体管和基极端子连接到偏置源的双极晶体管，并且其选择来自 将高电压源提供给低电压源; MOS晶体管，其导通通过流过所述双极晶体管之一的集电极端子的电流来控制; 连接在高电压源和输出端子之间的P沟道MOS型晶体管，其导通由流过所述双极晶体管的另一个的集电极端子的集电极端电流或通过在 所述MOS晶体管的源极端子和漏极端子; 以及连接在低电压源和输出端子之间的N沟道型MOS晶体管，其导通被控制在集电极端子电流或所述漏极端子电流之间。