Semiconductor device and semiconductor memory device

    公开(公告)号:US11502204B2

    公开(公告)日:2022-11-15

    申请号:US17447330

    申请日:2021-09-10

    Abstract: Provided is a semiconductor device of the embodiment including: an oxide semiconductor layer; a gate electrode; a first electrode electrically connected to one portion of the oxide semiconductor layer, the first electrode including a first region, second region, a third region, and a fourth region, the first region disposed between the first portion and the second region, the first region disposed between the third region and the fourth region, the first region containing at least one element of In, Zn, Sn or Cd, and oxygen, the second region containing at least one metal element of Ti, Ta, W, or Ru, the third region and the fourth region containing the at least one metal element and oxygen, the third region and the fourth region having an atomic concentration of oxygen higher than that of the second region; and a second electrode electrically connected to another portion of the oxide semiconductor layer.

    Semiconductor device and semiconductor memory device

    公开(公告)号:US11978807B2

    公开(公告)日:2024-05-07

    申请号:US17964375

    申请日:2022-10-12

    Abstract: Provided is a semiconductor device of the embodiment including: an oxide semiconductor layer; a gate electrode; a first electrode electrically connected to one portion of the oxide semiconductor layer, the first electrode including a first region, second region, a third region, and a fourth region, the first region disposed between the first portion and the second region, the first region disposed between the third region and the fourth region, the first region containing at least one element of In, Zn, Sn or Cd, and oxygen, the second region containing at least one metal element of Ti, Ta, W, or Ru, the third region and the fourth region containing the at least one metal element and oxygen, the third region and the fourth region having an atomic concentration of oxygen higher than that of the second region; and a second electrode electrically connected to another portion of the oxide semiconductor layer.

    Method for manufacturing semiconductor device

    公开(公告)号:US10985027B2

    公开(公告)日:2021-04-20

    申请号:US16820888

    申请日:2020-03-17

    Abstract: A method for manufacturing a semiconductor device according to an embodiment includes: forming a first layer on a semiconductor substrate, a surface of the first layer having a first plane of which distance from the semiconductor substrate is a first distance and a second plane of which distance from the semiconductor substrate is a second distance smaller than the first distance, and a difference between the first distance and the second distance being 30 nm or more; performing planarization processing on the first layer to have the difference of less than 30 nm; forming a second layer directly on the first layer after performing the planarization processing; supplying a resist to the second layer; bringing a template having a pattern into contact with the resist to form a resist layer to which the pattern has been transferred; and etching the second layer using the resist layer as a mask.

    Semiconductor device and semiconductor memory device

    公开(公告)号:US11349033B2

    公开(公告)日:2022-05-31

    申请号:US17022328

    申请日:2020-09-16

    Abstract: A semiconductor device of an embodiment includes a first electrode, a second electrode, a first metallic region provided between the first electrode and the second electrode and includes at least one metallic element selected from the group consisting of indium (In), gallium (Ga), zinc (Zn), aluminum (Al), magnesium (Mg), manganese (Mn), titanium (Ti), tungsten (W), molybdenum (Mo), and tin (Sn), a second metallic region provided between the first metallic region and the second electrode and includes the at least one metallic element, a semiconductor region provided between the first metallic region and the second metallic region and includes the at least one metallic element and oxygen (O), an insulating region provided between the first metallic region and the second metallic region and is surrounded by the semiconductor region, a gate electrode surrounding the semiconductor region, and a gate insulating layer provided between the semiconductor region and the gate electrode.

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