公开(公告)号：US5910675A

公开(公告)日：1999-06-08

申请号：US763513

申请日：1996-12-11

申请人： Yoko Horiguchi ,  Kaoru Narita ,  Takeo Fujii

发明人： Yoko Horiguchi ,  Kaoru Narita ,  Takeo Fujii

IPC分类号： H01L27/02 ,  H01L27/06 ,  H01L29/72

CPC分类号： H01L27/0248 ,  H01L27/0635

摘要： A semiconductor device includes a metal terminal provided on a semiconductor substrate and a protection element. The protection element includes an insulated gate field-effect transistor. The transistor has a first diffusion layer of a reverse conductive-type formed on one conductive type region of the semiconductor substrate and connected to the metal terminal, as its source. The transistor also includes a second diffusion layer of a reverse conductive-type connected to an electrode wire having a constant electric potential, as its source, and has a gate electrode connected to the electrode wire. A lateral bipolar transistor includes a third diffusion layer of a reverse conductive-type formed with a constant spaced distance with respect to the second diffusion layer and connected to the metal terminal, as its collector, and also has the second diffusion layer as its emitter, and furthermore has the one conductive-type region as its base. Thus, a semiconductor device is protected from an electrostatic discharge (ESD) breakdown device even though having high density and a high operating speed.

摘要翻译： 半导体器件包括设置在半导体衬底上的金属端子和保护元件。 保护元件包括绝缘栅场效应晶体管。 晶体管具有形成在半导体衬底的一个导电类型区域上并以金属端子连接的反向导电型的第一扩散层作为其源极。 晶体管还包括连接到具有恒定电位的电极线作为其源极的反向导电型的第二扩散层，并且具有连接到电极线的栅电极。 横向双极晶体管包括反向导电型的第三扩散层，该第三扩散层相对于第二扩散层具有恒定的间隔距离并且连接到作为其集电极的金属端子，并且还具有第二扩散层作为其发射极， 并且还具有一个导电型区域作为其基底。 因此，即使具有高密度和高操作速度，半导体器件也被保护免受静电放电（ESD）击穿器件的影响。

公开(公告)号：US06191633B1

公开(公告)日：2001-02-20

申请号：US09149115

申请日：1998-09-09

申请人： Takeo Fujii ,  Kaoru Narita ,  Yoko Horiguchi

发明人： Takeo Fujii ,  Kaoru Narita ,  Yoko Horiguchi

IPC分类号： H03K508

CPC分类号： H03K5/08 ,  H01L27/0251 ,  H01L27/0255 ,  H01L27/0288 ,  H01L2924/0002 ,  H01L2924/00

摘要： A Semiconductor integrated circuit with a protection circuit against electrostatic discharge. A clamping element is connected with MIS transistor to prevent the breakdown under the charged device model. A parasitic bipolar transistor, a MOS transistor or MIS transistor whose gate is composed of an insulating film thicker than that of the transfer gate, can be used as the clamping element.

摘要翻译： 一个具有防静电放电保护电路的半导体集成电路。 夹紧元件与MIS晶体管连接，以防止充电器件型号下的击穿。 可以使用寄生双极晶体管，MOS晶体管或MIS晶体管，其栅极由比传输栅极厚的绝缘膜构成，可用作夹紧元件。

公开(公告)号：US06175139B1

公开(公告)日：2001-01-16

申请号：US09192473

申请日：1998-11-17

申请人： Yoko Horiguchi ,  Kaoru Narita ,  Takeo Fujii

发明人： Yoko Horiguchi ,  Kaoru Narita ,  Takeo Fujii

IPC分类号： H01L2972

CPC分类号： H01L27/0248 ,  H01L27/0635

摘要： A semiconductor device includes a metal terminal provided on a semiconductor substrate and a protection element. The protection element includes an insulated gate field-effect transistor. The transistor has a first diffusion layer of a reverse conductive-type formed on one conductive type region of the semiconductor substrate and connected to the metal terminal, as its source. The transistor also includes a second diffusion layer of a reverse conductive-type connected to an electrode wire having a constant electric potential, as its source, and has a gate electrode connected to the electrode wire. A lateral bipolar transistor includes a third diffusion layer of a reverse conductive-type formed with a constant spaced distance with respect to the second diffusion layer and connected to the metal terminal, as its collector, and also has the second diffusion layer as its emitter, and furthermore has the one conductive-type region as its base. Thus, a semiconductor device is protected from an electrostatic discharge (ESD) breakdown device even though having high density and a high operating speed.

摘要翻译： 半导体器件包括设置在半导体衬底上的金属端子和保护元件。 保护元件包括绝缘栅场效应晶体管。 晶体管具有形成在半导体衬底的一个导电类型区域上并以金属端子连接的反向导电型的第一扩散层作为其源极。 晶体管还包括连接到具有恒定电位的电极线作为其源极的反向导电型的第二扩散层，并且具有连接到电极线的栅电极。 横向双极晶体管包括反向导电型的第三扩散层，该第三扩散层相对于第二扩散层具有恒定的间隔距离并且连接到作为其集电极的金属端子，并且还具有第二扩散层作为其发射极， 并且还具有一个导电型区域作为其基底。 因此，即使具有高密度和高操作速度，半导体器件也被保护免受静电放电（ESD）击穿器件的影响。

公开(公告)号：US6101078A

公开(公告)日：2000-08-08

申请号：US149112

申请日：1998-09-09

申请人： Takeo Fujii ,  Kaoru Narita ,  Yoko Horiguchi

发明人： Takeo Fujii ,  Kaoru Narita ,  Yoko Horiguchi

IPC分类号： H01L23/495 ,  H01L23/60 ,  H01L27/02 ,  H02H9/04 ,  H02H3/00

CPC分类号： H01L24/06 ,  H01L23/4951 ,  H01L23/60 ,  H01L27/0248 ,  H02H9/046 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/12036 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30107

摘要： A lead on chip (LOC) semiconductor device or a chip on lead (COL) semiconductor device with a protection circuit. Non-connection pins are made shorter than connection pins to reduce the inductance of the non-connection pins, or to obtain a different capability of the protection circuit for non-connection pins with respect to connection pins. The time constant of the protection circuit for the non-connection pins is made longer than that of the protection circuit for the connection pins. Further, the clamping capability for the connection pins is made greater than that for another connection pin adjacent to the connection pin.

摘要翻译： 具有保护电路的片上芯片（LOC）半导体器件或引线（COL）半导体器件芯片。 非连接引脚比连接引脚短，以减少非连接引脚的电感，或者获得与连接引脚相关的非连接引脚的保护电路的不同能力。 非连接引脚的保护电路的时间常数比连接引脚的保护电路的时间常数长。 此外，连接销的夹紧能力大于与连接销相邻的另一个连接销的夹紧能力。

公开(公告)号：US5936283A

公开(公告)日：1999-08-10

申请号：US906336

申请日：1997-08-05

申请人： Kaoru Narita ,  Takeo Fujii

发明人： Kaoru Narita ,  Takeo Fujii

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8234 ,  H01L23/62 ,  H01L27/02 ,  H01L27/04 ,  H01L27/088 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L23/48

CPC分类号： H01L29/456 ,  H01L21/32053 ,  H01L23/62 ,  H01L27/0266 ,  H01L27/0288 ,  H01L29/41725 ,  H01L2924/0002

摘要： According to the present invention, a MOSFET for an input/output protective circuit in which a source diffusion layer, a drain diffusion layer and a gate electrode are formed on a semiconductor substrate comprises a high melting point metal silicide layer disposed on the drain diffusion layer through a first insulating film, a metal wire layer disposed on the high melting point metal silicide layer through a second insulating film, at least two first contact holes for electrically connecting the high melting point metal silicide layer and the metal wire layer, and a second contact hole for electrically connecting the high melting point metal silicide layer and the drain diffusion layer, wherein the second contact hole is disposed at a substantial center between the two first contact holes.

摘要翻译： 根据本发明，用于输入/输出保护电路的MOSFET，其中在半导体衬底上形成源极扩散层，漏极扩散层和栅极电极包括设置在漏极扩散层上的高熔点金属硅化物层 通过第一绝缘膜，通过第二绝缘膜设置在高熔点金属硅化物层上的金属线层，用于电连接高熔点金属硅化物层和金属线层的至少两个第一接触孔，以及第二绝缘膜 接触孔，用于电连接高熔点金属硅化物层和漏极扩散层，其中第二接触孔设置在两个第一接触孔之间的实质中心处。

公开(公告)号：US06275367B1

公开(公告)日：2001-08-14

申请号：US09323518

申请日：1999-06-01

申请人： Kaoru Narita ,  Takeo Fujii

发明人： Kaoru Narita ,  Takeo Fujii

IPC分类号： H02H320

CPC分类号： H01L27/0248

摘要： In a semiconductor circuit device, an internal circuit, a common wiring pattern, a plurality of external terminals including a ground terminal, and a plurality of protection elements is provided. Each of the plurality of protection elements is connected to one of the plurality of external terminals and the common wiring pattern. Each protection element includes a clamp circuit. The clamp circuit of each of the plurality of protection elements respectively connected to the plurality of external terminals other than the ground terminal has a clamp voltage higher than a power supply voltage supplied to the internal circuit. On the other hand, the clamp circuit of the protection element connected to the ground terminal as a ground terminal clamp circuit has a clamp voltage lower than those of the clamp circuits other than the ground terminal clamp circuit.

摘要翻译： 在半导体电路装置中，设置有内部电路，公共布线图案，包括接地端子的多个外部端子以及多个保护元件。 多个保护元件中的每一个连接到多个外部端子和公共布线图案中的一个。 每个保护元件包括钳位电路。 分别连接到除了接地端子之外的多个外部端子的多个保护元件中的每一个的钳位电路具有高于提供给内部电路的电源电压的钳位电压。 另一方面，与作为接地端子钳位电路的接地端子连接的保护元件的钳位电路的钳位电压比除接地端子钳位电路以外的钳位电路的钳位电压低。

公开(公告)号：US5973901A

公开(公告)日：1999-10-26

申请号：US904917

申请日：1997-08-01

申请人： Kaoru Narita ,  Takeo Fujii

发明人： Kaoru Narita ,  Takeo Fujii

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H02H3/22

CPC分类号： H01L27/0248

摘要： In a semiconductor circuit device, an internal circuit, a common wiring pattern, a plurality of external terminals including a ground terminal, and a plurality of protection elements is provided. Each of the plurality of protection elements is connected to one of the plurality of external terminals and the common wiring pattern. Each protection element includes a clamp circuit. The clamp circuit of each of the plurality of protection elements respectively connected to the plurality of external terminals other than the ground terminal has a clamp voltage higher than a power supply voltage supplied to the internal circuit. On the other hand, the clamp circuit of the protection element connected to the ground terminal as a ground terminal clamp circuit has a clamp voltage lower than those of the clamp circuits other than the ground terminal clamp circuit.

摘要翻译： 在半导体电路装置中，设置有内部电路，公共布线图案，包括接地端子的多个外部端子以及多个保护元件。 多个保护元件中的每一个连接到多个外部端子和公共布线图案中的一个。 每个保护元件包括钳位电路。 分别连接到除了接地端子之外的多个外部端子的多个保护元件中的每一个的钳位电路具有高于提供给内部电路的电源电压的钳位电压。 另一方面，与作为接地端子钳位电路的接地端子连接的保护元件的钳位电路的钳位电压比除接地端子钳位电路以外的钳位电路的钳位电压低。

公开(公告)号：US07750765B2

公开(公告)日：2010-07-06

申请号：US12249273

申请日：2008-10-10

申请人： Taras Kushta ,  Kaoru Narita ,  Takanori Saeki ,  Tomoyuki Kaneko ,  Hirokazu Tohya

发明人： Taras Kushta ,  Kaoru Narita ,  Takanori Saeki ,  Tomoyuki Kaneko ,  Hirokazu Tohya

IPC分类号： H03H7/38 ,  H01P1/04

CPC分类号： H05K1/0222 ,  H01P3/06 ,  H05K1/024 ,  H05K1/0251 ,  H05K3/429 ,  H05K2201/0187 ,  H05K2201/09063 ,  H05K2201/09536 ,  H05K2201/09618 ,  H05K2201/09718 ,  H05K2201/09809

摘要： A compact via transmission line for a printed circuit board having preferred characteristic impedance and capable of miniaturizing the printed circuit board including a multilayer printed circuit board, and extending the frequency range of a via transmission line mounted on the printed circuit board, and a design method of the same. The transmission line has a central conductor forming an inner conductor layer boundary make up a signal via hole, a plurality of via holes arranged around the central conductor form an outer conductor layer boundary, and a plurality of conductor plates formed of a printed circuit board conductor layer, is further provided with a constitutive parameter adjustment clearance hole between the inner and outer conductor layer boundaries of the compact via transmission line, and electrically isolates to prevent cross-talk of a signal propagating through a signal via hole with other signals in a high-frequency signal band.

摘要翻译： 一种用于具有优选特性阻抗并能够使包括多层印刷电路板的印刷电路板小型化并且扩展安装在印刷电路板上的通孔传输线的频率范围的印刷电路板的紧凑型通路传输线，以及设计方法 一样的。 传输线具有形成内导体层边界的中心导体，构成信号通孔，围绕中心导体布置的多个通孔形成外导体层边界，以及由印刷电路板导体形成的多个导体板 通过传输线在压缩体的内部和外部导体层边界之间进一步设置本构参数调整间隙孔，并且电隔离以防止通过信号通孔传播的信号与其他信号在高电平中的串扰 频率信号频带。

公开(公告)号：US5521413A

公开(公告)日：1996-05-28

申请号：US346307

申请日：1994-11-23

申请人： Kaoru Narita

发明人： Kaoru Narita

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L23/485 ,  H01L27/06 ,  H01L29/74 ,  H01L23/62 ,  H02H3/20

CPC分类号： H01L23/485 ,  H01L2924/0002

摘要： On the surface of a p-type semiconductor substrate, an n-type diffusion layer is formed. The diffusion layer is in contact with an aluminum wiring via a contact hole formed through an interlayer insulation layer to electrical connection. Immediately beneath the contact portion of the aluminum wiring, a contact n-type diffusion layer having higher impurity concentration than the n-type diffusion layer and having deeper junction depth. Outside of the contact n-type diffusion layer is surrounded by a low impurity concentration n well. With the construction, when an electrostatic pulse is applied to an external terminal connected to the shallow diffusion layer, junction breakdown of the diffusion layer can be successfully prevented.

摘要翻译： 在p型半导体衬底的表面上形成n型扩散层。 扩散层通过形成在层间绝缘层上的接触孔与铝布线接触以进行电连接。 在铝布线的接触部分的正下方，具有比n型扩散层更高的杂质浓度并且具有更深的结深度的接触n型扩散层。 在接触n型扩散层外面被低杂质浓度n阱包围。 利用这种结构，当静电脉冲施加到连接到浅扩散层的外部端子时，可以成功地防止扩散层的结击穿。

公开(公告)号：US5436487A

公开(公告)日：1995-07-25

申请号：US248729

申请日：1994-05-25

申请人： Kaoru Narita

发明人： Kaoru Narita

IPC分类号： H01L21/822 ,  G11C11/409 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/06 ,  H01L27/088 ,  H01L29/78 ,  H03K5/02 ,  H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  H03K19/094 ,  H01L27/02 ,  H01L29/72

CPC分类号： H03K19/09403 ,  H03K19/00315 ,  H03K19/00361

摘要： In an output circuit having first and second MOS transistors in series between a first power supply line and a second power supply line, and a third MOS transistor, the gates of the first and second transistors are connected to first and second input nodes, respectively, and an output node is provided between the first and second MOS transistors. The third MOS transistor is connected between one of the input nodes and the output node. The gate of the third MOS transistor is connected to a third power supply line.

摘要翻译： 在具有串联在第一电源线和第二电源线之间的第一和第二MOS晶体管和第三MOS晶体管的输出电路中，第一和第二晶体管的栅极分别连接到第一和第二输入节点， 并且在第一和第二MOS晶体管之间提供输出节点。 第三MOS晶体管连接在输入节点之一和输出节点之间。 第三MOS晶体管的栅极连接到第三电源线。