公开(公告)号：US06850963B1

公开(公告)日：2005-02-01

申请号：US09655492

申请日：2000-09-05

申请人： Kazuhiro Adachi ,  Masahiro Akahori ,  Katsuhisa Fukuda ,  Takahiro Yoshida

发明人： Kazuhiro Adachi ,  Masahiro Akahori ,  Katsuhisa Fukuda ,  Takahiro Yoshida

IPC分类号： G06Q30/00 ,  G06F15/16

CPC分类号： G06Q30/06

摘要： An information service providing method for providing an information service is provided, wherein the method includes the steps of: receiving a customer's request for the information service to be provided with; deciding the customer's utilization qualification with respect to the contents of the information service; determining the contents that is available to the customer according to the customer's utilization qualification among the contents of the information service that the customer requests to be provided with; and providing the customer with the determined contents of the information service.

摘要翻译： 提供一种用于提供信息服务的信息服务提供方法，其中该方法包括以下步骤：接收客户对要提供的信息服务的请求; 决定客户对信息服务内容的使用资格; 根据客户要求提供的信息服务的内容之间的客户使用资格确定客户可用的内容; 并向客户提供确定的信息服务内容。

公开(公告)号：US08952391B2

公开(公告)日：2015-02-10

申请号：US10531582

申请日：2003-10-03

申请人： Shinsuke Harada ,  Tsutomu Yatsuo ,  Kenji Fukuda ,  Mitsuo Okamoto ,  Kazuhiro Adachi ,  Seiji Suzuki

发明人： Shinsuke Harada ,  Tsutomu Yatsuo ,  Kenji Fukuda ,  Mitsuo Okamoto ,  Kazuhiro Adachi ,  Seiji Suzuki

IPC分类号： H01L29/15 ,  H01L29/66 ,  H01L21/04 ,  H01L29/78 ,  H01L21/02 ,  H01L29/10 ,  H01L29/16 ,  H01L29/423

CPC分类号： H01L29/66477 ,  H01L21/02529 ,  H01L21/0465 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/7802

摘要： A silicon carbide vertical MOSFET having low ON-resistance and high blocking voltage. A first deposition film of low concentration silicon carbide of a first conductivity type is formed on the surface of a high concentration silicon carbide substrate of a first conductivity type. Formed on the first deposition film is a second deposition film that includes a high concentration gate region of a second conductivity type, with a first region removed selectively. A third deposition film is formed on the second deposition film, which includes a second region that is wider than the selectively removed first region, a high concentration source region of a first conductivity type, and a low concentration gate region of a second conductivity type. A low concentration base region of a first conductivity type is formed in contact with the first deposition film in the first and second regions.

摘要翻译： 具有低导通电阻和高阻断电压的碳化硅垂直MOSFET。 在第一导电类型的高浓度碳化硅衬底的表面上形成第一导电类型的低浓度碳化硅的第一沉积膜。 形成在第一沉积膜上的是第二沉积膜，其包括第二导电类型的高浓度栅极区域，其中第一区域被选择性地去除。 在第二沉积膜上形成第三沉积膜，其包括比选择性去除的第一区域宽的第二区域，第一导电类型的高浓度源区域和第二导电类型的低浓度栅极区域。 第一导电类型的低浓度基区形成为与第一和第二区域中的第一沉积膜接触。

公开(公告)号：US06812102B2

公开(公告)日：2004-11-02

申请号：US10466311

申请日：2003-12-30

申请人： Kenji Fukuda ,  Kazuo Arai ,  Junji Senzaki ,  Shinsuke Harada ,  Ryoji Kosugi ,  Kazuhiro Adachi ,  Seiji Suzuki

发明人： Kenji Fukuda ,  Kazuo Arai ,  Junji Senzaki ,  Shinsuke Harada ,  Ryoji Kosugi ,  Kazuhiro Adachi ,  Seiji Suzuki

IPC分类号： H01L21336

CPC分类号： H01L29/66068 ,  H01L21/049 ,  H01L29/1608 ,  H01L29/7838

摘要： In a semiconductor device using a silicon carbide substrate (1), the object of the present invention is to provide a method of manufacturing a semiconductor device that is a buried channel region type transistor having hot-carrier resistance, high punch-through resistance and high channel mobility. This is achieved by using a method of manufacturing a buried channel type transistor using a P-type silicon carbide substrate that includes a step of forming a buried channel region, a source region and a drain region, a step of forming a gate insulation layer after the step of forming the buried channel region, source region and drain region, and a step of exposing the gate insulation layer to an atmosphere containing water vapor at a temperature of 500° C. or more after the step of forming the gate insulation layer. The gate insulation layer is formed by a thermal oxidation method using dry oxygen.

公开(公告)号：US08525239B2

公开(公告)日：2013-09-03

申请号：US13390613

申请日：2011-05-24

申请人： Koutarou Tanaka ,  Takashi Hori ,  Kazuhiro Adachi

发明人： Koutarou Tanaka ,  Takashi Hori ,  Kazuhiro Adachi

IPC分类号： H01L29/772

CPC分类号： H01L29/7838 ,  H01L29/1033 ,  H01L29/1608 ,  H01L29/7828

摘要： The present invention is directed to an MIS type semiconductor device, including a channel layer between a semiconductor body region and a gate insulating film, the channel layer having an opposite semiconductor polarity to that of the semiconductor body region. Since Vfb of the semiconductor device is equivalent to or less than a gate rated voltage Vgcc− of the semiconductor device with respect to an OFF-polarity, density of carrier charge that is induced near the surface of the semiconductor body region is kept at a predetermined amount or less with a guaranteed range of operation of the semiconductor device.

摘要翻译： 本发明涉及一种MIS半导体器件，其包括在半导体主体区域和栅极绝缘膜之间的沟道层，沟道层具有与半导体本体区域相反的半导体极性。 由于半导体器件的Vfb相对于OFF极性等于或小于半导体器件的栅极额定电压Vgcc-，所以在半导体本体区域的表面附近感应的载流子电荷的密度保持在预定的 数量或更少，具有半导体器件的有保证的操作范围。

公开(公告)号：US08471267B2

公开(公告)日：2013-06-25

申请号：US13129825

申请日：2010-08-26

申请人： Masashi Hayashi ,  Koichi Hashimoto ,  Kazuhiro Adachi

发明人： Masashi Hayashi ,  Koichi Hashimoto ,  Kazuhiro Adachi

IPC分类号： H01L29/12 ,  H01L21/31

CPC分类号： H01L29/66068 ,  H01L21/045 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device of the present invention has a semiconductor element region 17 that is provided in part of a silicon carbide layer 3 and a guard-ring region 18 that is provided in another part of the silicon carbide layer 3 surrounding the semiconductor element region 17 when seen in a direction perpendicular to a principal surface of the silicon carbide layer 3. The semiconductor device includes: an interlayer insulation film 10 which is provided on the principal surface of the silicon carbide layer 3 in the semiconductor element region 17 and the guard-ring region 18, the interlayer insulation film 10 having a relative dielectric constant of 20 or more; a first protective insulation film 14 provided on the interlayer insulation film in the guard-ring region 18; and a second protective insulation film 15 provided on the first protective insulation film 14, wherein the first protective insulation film 14 has a linear expansion coefficient which is between a linear expansion coefficient of a material of the second protective insulation film 15 and a linear expansion coefficient of a material of the interlayer insulation film 10.

摘要翻译： 本发明的半导体器件具有半导体元件区域17，该半导体元件区域17设置在碳化硅层3的一部分和保护环区域18之间，该保护环区域设置在围绕半导体元件区域17的碳化硅层3的另一部分中， 在与碳化硅层3的主表面垂直的方向上观察。半导体器件包括：层间绝缘膜10，其设置在半导体元件区域17中的碳化硅层3的主表面上，保护环 区域18，相对介电常数为20以上的层间绝缘膜10; 设置在保护环区域18中的层间绝缘膜上的第一保护绝缘膜14; 以及设置在第一保护绝缘膜14上的第二保护绝缘膜15，其中第一保护绝缘膜14具有在第二保护绝缘膜15的材料的线膨胀系数与线膨胀系数之间的线性膨胀系数 的层间绝缘膜10的材料。

公开(公告)号：US08429443B2

公开(公告)日：2013-04-23

申请号：US13086726

申请日：2011-04-14

申请人： Tetsuhiro Goto ,  Kazuhiro Adachi

发明人： Tetsuhiro Goto ,  Kazuhiro Adachi

IPC分类号： G06F11/00

CPC分类号： G06F11/2023 ,  G06F9/4401 ,  G06F11/1076 ,  G06F11/2025 ,  G06F11/2028 ,  G06F11/2046 ,  H04L29/12594 ,  H04L29/12886 ,  H04L41/06 ,  H04L61/30 ,  H04L61/6045 ,  H04L67/1097 ,  H04L69/40

摘要： When a primary computer is taken over to a secondary computer in a redundancy configuration computer system where booting is performed via a storage area network (SAN), a management server delivers an information collecting/setting program to the secondary computer before the user's operating system of the secondary computer is started. This program assigns a unique ID (World Wide Name), assigned to the fiber channel port of the primary computer, to the fiber channel port of the secondary computer to allow a software image to be taken over from the primary computer to the secondary computer.

摘要翻译： 当主计算机被接管到通过存储区域网络（SAN）执行引导的冗余配置计算机系统中的次计算机时，管理服务器在用户的操作系统的操作系统之前将信息收集/设置程序传送到次计算机 辅助计算机启动。 该程序将分配给主计算机的光纤通道端口的唯一ID（万维网名称）分配给辅助计算机的光纤通道端口，以允许将软件映像从主计算机接管到辅助计算机。

公开(公告)号：US20120139623A1

公开(公告)日：2012-06-07

申请号：US13389555

申请日：2010-08-09

申请人： Koichi Hashimoto ,  Kazuhiro Adachi ,  Osamu Kusumoto ,  Masao Uchida ,  Shun Kazama

发明人： Koichi Hashimoto ,  Kazuhiro Adachi ,  Osamu Kusumoto ,  Masao Uchida ,  Shun Kazama

IPC分类号： G05F3/02 ,  H01L29/78

CPC分类号： H01L29/7828 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7838 ,  H02M7/5387 ,  Y02B70/1483

摘要： A semiconductor element 100 including an MISFET according to the present invention is characterized by having diode characteristics in a reverse direction through an epitaxial channel layer 50. The semiconductor element 100 includes a semiconductor layer 20 of a first conductivity type, a body region 30 of a second conductivity type, source and drain regions 40 and 75 of the first conductivity type, an epitaxial channel layer 50 in contact with the body region, source and drain electrodes 45 and 70, a gate insulating film 60, and a gate electrode 65. If the voltage applied to the gate electrode of the MISFET is smaller than a threshold voltage, the semiconductor element 100 functions as a diode in which current flows from the source electrode 45 to the drain electrode 70 through the epitaxial channel layer 50. The absolute value of the turn-on voltage of this diode is smaller than that of the turn-on voltage of a body diode that is formed of the body region and the first silicon carbide semiconductor layer.

摘要翻译： 包括根据本发明的MISFET的半导体元件100的特征在于通过外延沟道层50在相反方向上具有二极管特性。半导体元件100包括第一导电类型的半导体层20，第一导电类型的体区30 第二导电类型，第一导电类型的源极和漏极区域40和75，与主体区域接触的外延沟道层50，源极和漏极电极45和70，栅极绝缘膜60和栅电极65.如果 施加到MISFET的栅电极的电压小于阈值电压，半导体元件100用作二极管，其中电流通过外延沟道层50从源电极45流到漏极70。绝对值 该二极管的导通电压小于由体区和第一硅碳化物形成的体二极管的导通电压的导通电压 e半导体层。

公开(公告)号：US20130285650A1

公开(公告)日：2013-10-31

申请号：US13979727

申请日：2012-02-20

申请人： Kazuhiro Adachi ,  Kyoichi Okamura ,  Koji Kawasaki

发明人： Kazuhiro Adachi ,  Kyoichi Okamura ,  Koji Kawasaki

IPC分类号： G01P3/44 ,  B29C45/14

CPC分类号： G01P3/44 ,  B29C45/14 ,  F16C41/007 ,  G01P3/443 ,  G01P3/487

摘要： A rotation speed detecting apparatus, including: an annular fixing member to be fixed to a support member configured to rotatably support a rotating object to be detected; a case mounted to the fixing member; a detecting portion abutting against an abutment portion provided in the case so as to be positioned with respect to the case for detecting a rotation speed of the rotating object to be detected; and a resin mold portion formed by resin molding and configured to fix the detecting portion to the case in a state in which the detecting portion abuts against the abutment portion of the case.

摘要翻译： 一种转速检测装置，包括：环形固定构件，其被固定到支撑构件，所述支撑构件构造成可旋转地支撑待检测的旋转物体; 安装到所述固定构件的壳体; 检测部，其抵靠设置在所述壳体中的抵接部，以相对于所述壳体定位，用于检测所述待检测的旋转物体的旋转速度; 以及树脂模制部，其通过树脂成型形成，并且被构造成在所述检测部抵接在所述壳体的抵接部的状态下将所述检测部固定在所述壳体上。

公开(公告)号：US08432039B2

公开(公告)日：2013-04-30

申请号：US12974230

申请日：2010-12-21

申请人： Katsuhiko Maki ,  Kazuhiro Adachi

发明人： Katsuhiko Maki ,  Kazuhiro Adachi

IPC分类号： H01L23/485 ,  H01L23/64

CPC分类号： H01L24/06 ,  H01L23/5223 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/60 ,  H01L27/0203 ,  H01L27/0255 ,  H01L27/092 ,  H01L27/105 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05624 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/3025 ,  H03F3/45188 ,  H03F2203/45631 ,  H03F2203/45704

摘要： An integrated circuit device includes a receiving circuit, a transmission circuit, and common pads common to the receiving circuit and the transmission circuit, which are disposed in such a way that the distance between the receiving circuit and the common pad, and the distance between the transmission circuit and the common pad become shorter, respectively.

摘要翻译： 集成电路装置包括接收电路，发送电路和接收电路和传输电路共同的公共衬垫，其以这样的方式设置，使得接收电路和公共衬垫之间的距离和 传输电路和公共焊盘分别变短。

公开(公告)号：US08410489B2

公开(公告)日：2013-04-02

申请号：US13266271

申请日：2010-04-28

申请人： Kazuhiro Adachi ,  Osamu Kusumoto ,  Masao Uchida ,  Koichi Hashimoto ,  Shun Kazama

发明人： Kazuhiro Adachi ,  Osamu Kusumoto ,  Masao Uchida ,  Koichi Hashimoto ,  Shun Kazama

IPC分类号： H01L29/24

CPC分类号： H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/7805 ,  H01L29/7827 ,  H01L29/7828 ,  H03K17/145

摘要： A semiconductor element 100 including an MISFET according to the present invention is characterized by having diode characteristics in a reverse direction through an epitaxial channel layer 50. The semiconductor element 100 includes a silicon carbide semiconductor substrate 10 of a first conductivity type, a semiconductor layer 20 of the first conductivity type, a body region 30 of a second conductivity type, a source region 40 of the first conductivity type, an epitaxial channel layer 50 in contact with the body region, a source electrode 45, a gate insulating film 60, a gate electrode 65 and a drain electrode 70. If the voltage applied to the gate electrode of the MISFET is smaller than a threshold voltage, the semiconductor element 100 functions as a diode in which current flows from the source electrode 45 to the drain electrode 70 through the epitaxial channel layer 50. The absolute value of the turn-on voltage of this diode is smaller than that of the turn-on voltage of a body diode that is formed of the body region and the first silicon carbide semiconductor layer.

摘要翻译： 包括根据本发明的MISFET的半导体元件100的特征在于通过外延沟道层50在相反方向上具有二极管特性。半导体元件100包括第一导电类型的碳化硅半导体衬底10，半导体层20 第一导电类型的体区30，第一导电类型的源极区40，与体区接触的外延沟道层50，源电极45，栅极绝缘膜60， 栅电极65和漏电极70.如果施加到MISFET的栅电极的电压小于阈值电压，则半导体元件100用作二极管，其中电流从源电极45流到漏电极70通过 外延沟道层50.该二极管的导通电压的绝对值小于体二的导通电压的绝对值 由所述体区和所述第一碳化硅半导体层形成。