公开(公告)号：US4998155A

公开(公告)日：1991-03-05

申请号：US73305

申请日：1987-07-13

申请人： Kikuo Watanabe ,  Tohru Nakamura ,  Toru Toyabe ,  Takahiro Okabe ,  Minoru Nagata

发明人： Kikuo Watanabe ,  Tohru Nakamura ,  Toru Toyabe ,  Takahiro Okabe ,  Minoru Nagata

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L29/08 ,  H01L29/10 ,  H01L29/72 ,  H01L29/732

CPC分类号： H01L29/1008 ,  H01L29/1004 ,  H01L29/72 ,  Y10S257/906

摘要： A radiation-hardened semiconductor device including a bipolar transistor is disclosed in which a highly-doped layer equal in conductivity type to and larger in impurity concentration than the base region of the transistor is formed in that portion of the surface of the base region which exists beneath an insulating film, to prevent minority carriers injected into the base region, from reaching the above-mentioned surface portion. Thus, the injected minority carriers can reach a collector region without being extinguished by the recombination at the surface of the base region.

摘要翻译： 公开了一种包括双极晶体管的辐射硬化半导体器件，其中在存在的基极区域的表面部分中形成了与晶体管的基极区相比导电类型等于或大于杂质浓度的高掺杂层 在绝缘膜下面，以防止注入基底区域的少数载流子到达上述表面部分。 因此，注入的少数载流子可以到达集电极区，而不会被基区表面的复合所熄灭。

公开(公告)号：US4429326A

公开(公告)日：1984-01-31

申请号：US96388

申请日：1979-11-21

申请人： Tomoyuki Watanabe ,  Kenji Kaneko ,  Tohru Nakamura ,  Yutaka Okada ,  Takahiro Okabe ,  Minoru Nagata ,  Yokichi Itoh ,  Toru Toyabe

发明人： Tomoyuki Watanabe ,  Kenji Kaneko ,  Tohru Nakamura ,  Yutaka Okada ,  Takahiro Okabe ,  Minoru Nagata ,  Yokichi Itoh ,  Toru Toyabe

IPC分类号： G11C11/411 ,  G11C14/00 ,  G11C16/04 ,  H01L27/02 ,  H01L27/07 ,  H01L27/102 ,  G11C11/40 ,  H01L27/04 ,  H01L29/78 ,  H03K19/091

CPC分类号： H01L27/0711 ,  G11C11/4113 ,  G11C14/00 ,  G11C16/0433 ,  G11C16/0466 ,  H01L27/0233 ,  H01L27/1022

摘要： An I.sup.2 L type nonvolatile memory of this invention has a structure wherein a floating gate is disposed through an insulating film on the surface of a semiconductor layer in the vicinity of a base region of an NPN transistor in an I.sup.2 L. The I.sup.2 L type nonvolatile memory of this invention controls current to flow through the base region of the NPN transistor of the I.sup.2 L, by means of charges to be stored in the floating gate. That is, the collector output current of the NPN transistor of the I.sup.2 L is modulated in dependence on the presence or absence of a channel underneath the floating gate as is generated depending on the presence or absence of charges within the floating gate and the polarity of the charges. As a result, the variation of the base current appears as an output signal at a collector terminal of the NPN transistor of the I.sup.2 L, and data stored in the floating gate can be read out.

摘要翻译： 本发明的I2L型非易失性存储器具有这样的结构，其中浮置栅极通过I2L中的NPN晶体管的基极区附近的半导体层的表面上的绝缘膜设置。 本发明的I2L型非易失性存储器通过要存储在浮动栅极中的电荷来控制电流流过I2L的NPN晶体管的基极区域。 也就是说，I2L的NPN晶体管的集电极输出电流根据浮置栅极下面的通道的存在或不存在而被调制，这取决于浮置栅极内的电荷的存在或不存在以及浮置栅极的极性 收费。 结果，基极电流的变化在I2L的NPN晶体管的集电极端子处显示为输出信号，并且可以读出存储在浮动栅极中的数据。

公开(公告)号：US06734501B2

公开(公告)日：2004-05-11

申请号：US10058221

申请日：2002-01-29

申请人： Takuo Sugano ,  Toru Toyabe ,  Tatsuro Hanajiri ,  Akira Saito ,  Yoshiro Akagi

发明人： Takuo Sugano ,  Toru Toyabe ,  Tatsuro Hanajiri ,  Akira Saito ,  Yoshiro Akagi

IPC分类号： H01L310392

CPC分类号： H01L29/78696 ,  H01L27/1203 ,  H01L29/458 ,  H01L29/66621 ,  H01L29/66772

摘要： A fully inverted type SOI-MOSFET has a channel region 18 constructed of a portion that belongs to a top silicon layer 13 and is located just under a gate electrode 15 and a source region 16 and a drain region 17, which belong to the top silicon layer 13 and are located adjacent to this channel region 18. The channel region 18 is inverted throughout the entire thickness during operation. The source region 16 has a source resistance RS, which satisfies a relation that (1/gm)>RS with respect to the mutual conductance gm of the channel region 18 itself. According to this fully inverted type SOI-MOSFET, the effective mutual conductance (Gm) can be increased.

摘要翻译： 全反相型SOI-MOSFET具有由属于顶部硅层13的部分构成的沟道区18，该沟道区18位于栅电极15的下方，源极区16和漏极区17属于顶部硅 层13并且位于该通道区域18附近。在操作期间，通道区域18在整个厚度上反转。 源极区域16具有源极电阻RS，其满足关于通道区域18本身的互导体gm的关系（1 / gm）> RS。 根据这种完全反转型的SOI-MOSFET，可以提高有效的互导（Gm）。

公开(公告)号：US20120025196A1

公开(公告)日：2012-02-02

申请号：US13263122

申请日：2010-01-18

申请人： Yasuo Wada ,  Toru Toyabe ,  Ken Tsutsui

发明人： Yasuo Wada ,  Toru Toyabe ,  Ken Tsutsui

IPC分类号： H01L51/10

CPC分类号： H01L51/002 ,  H01L51/0541 ,  H01L51/0545 ,  H01L51/105

摘要： An organic thin film transistor includes an organic semiconductor layer, a source electrode and a drain electrode which are separated from each other and are individually in contact with the organic semiconductor layer, a gate insulating film which is in contact with the organic semiconductor layer between the source and drain electrodes, and a gate electrode which is opposed to the organic semiconductor layer and is in contact with the gate insulating film. In the organic thin film transistor, a high-concentration region of the organic semiconductor layer which is located near the source electrode has an impurity concentration set higher than an impurity concentration of a low-concentration region of the organic semiconductor layer, the low-concentration region being located near the gate electrode in the thickness direction of the organic semiconductor layer between the source and drain electrodes.

摘要翻译： 有机薄膜晶体管包括彼此分离并分别与有机半导体层接触的有机半导体层，源电极和漏电极，在有机半导体层之间与有机半导体层接触的栅极绝缘膜 源极和漏极以及与有机半导体层相对并与栅极绝缘膜接触的栅电极。 在有机薄膜晶体管中，位于源电极附近的有机半导体层的高浓度区域的杂质浓度设定为高于有机半导体层的低浓度区域的杂质浓度，低浓度 区域位于源极和漏极之间的有机半导体层的厚度方向上的栅电极附近。

公开(公告)号：US5258625A

公开(公告)日：1993-11-02

申请号：US961547

申请日：1992-10-15

申请人： Shiroo Kamohara ,  Toru Toyabe ,  Kozo Katayama ,  Shuichi Yamamoto ,  Sigeo Ihara

发明人： Shiroo Kamohara ,  Toru Toyabe ,  Kozo Katayama ,  Shuichi Yamamoto ,  Sigeo Ihara

IPC分类号： H01L21/82 ,  H01L21/8232 ,  H01L21/8244 ,  H01L27/06 ,  H01L27/095 ,  H01L27/10 ,  H01L27/11 ,  H01L27/118 ,  H01L29/66 ,  H01L29/68 ,  H01L29/72 ,  H01L29/762 ,  H01L29/80 ,  H01L29/88 ,  H03K19/02

CPC分类号： B82Y10/00 ,  B82Y30/00 ,  H01L27/118 ,  H01L29/72 ,  H01L29/762 ,  H01L29/88 ,  H03K19/02 ,  Y10S977/937

摘要： An interband single-electron tunnel transistor utilizes an interband single-electron tunneling phenomenon between a valence band and a conduction band through a p-n junction. The transistor includes the combination of microcapacities as fundamental constituent elements each formed by joining a p-type semiconductor material doped with an impurity in the degree of concentration with which a Fermi level overlaps a valence band and an n-type semiconductor material doped with an impurity in the degree of concentration with which the Fermi level overlaps a conduction band. The microcapacity includes a p-n junction having a junction area with which interband electron tunneling is inhibited due to Coulomb blockade.

摘要翻译： 带间单电子隧道晶体管利用通过p-n结的价带和导带之间的带间单电子隧道现象。 晶体管包括作为基本构成元件的微电容的组合，其通过将掺杂有杂质的p型半导体材料以费米能级与价带重叠的浓度与掺杂有杂质的n型半导体材料接合而形成 在费米能级与导带重叠的浓度下。 微容量包括具有结区的p-n结，由于库仑阻挡，带间电子隧道被阻止。

公开(公告)号：US5422496A

公开(公告)日：1995-06-06

申请号：US117801

申请日：1993-09-08

申请人： Shiroo Kamohara ,  Toru Toyabe ,  Kozo Katayama ,  Shuichi Yamamoto ,  Sigeo Ihara

发明人： Shiroo Kamohara ,  Toru Toyabe ,  Kozo Katayama ,  Shuichi Yamamoto ,  Sigeo Ihara

IPC分类号： H01L21/82 ,  H01L21/8232 ,  H01L21/8244 ,  H01L27/06 ,  H01L27/095 ,  H01L27/10 ,  H01L27/11 ,  H01L27/118 ,  H01L29/66 ,  H01L29/68 ,  H01L29/72 ,  H01L29/762 ,  H01L29/80 ,  H01L29/88 ,  H03K19/02

CPC分类号： B82Y10/00 ,  B82Y30/00 ,  H01L27/118 ,  H01L29/72 ,  H01L29/762 ,  H01L29/88 ,  H03K19/02 ,  Y10S977/937

摘要： An interband single-electron tunnel/transistor utilizes an interband single-electron tunneling phenomenon between a valence band and a conduction band through a p-n junction. The transistor includes the combination of microcapacities as fundamental constituent elements each formed by joining a p-type semiconductor material doped with an impurity in the degree of concentration with which a Fermi level overlaps a valence band and an n-type semiconductor material doped with an impurity in the degree of concentration with which the Fermi level overlaps a conduction band. The microcapacity includes a p-n junction having a junction area with which interband electron tunneling is inhibited due to Coulomb blockade.

摘要翻译： 带间单电子隧道/晶体管利用通过p-n结的价带和导带之间的带间单电子隧道现象。 晶体管包括作为基本构成元件的微电容的组合，其通过将掺杂有杂质的p型半导体材料以费米能级与价带重叠的浓度与掺杂有杂质的n型半导体材料接合而形成 在费米能级与导带重叠的浓度下。 微容量包括具有结区的p-n结，由于库仑阻挡，带间电子隧穿被阻止。

公开(公告)号：US5408116A

公开(公告)日：1995-04-18

申请号：US105330

申请日：1993-08-09

申请人： Junko Tanaka ,  Toru Toyabe ,  Shin'ichiro Kimura ,  Hiromasa Noda ,  Sigeo Ihara ,  Kiyoo Itoh ,  Yasushi Gotoh

发明人： Junko Tanaka ,  Toru Toyabe ,  Shin'ichiro Kimura ,  Hiromasa Noda ,  Sigeo Ihara ,  Kiyoo Itoh ,  Yasushi Gotoh

IPC分类号： H01L29/78 ,  B82B1/00 ,  H01L27/108 ,  H01L29/06 ,  H01L29/12 ,  H01L29/423

CPC分类号： H01L29/125 ,  B82Y10/00 ,  H01L27/10808 ,  H01L29/78

摘要： A finely structured grooved gate transistor of which the threshold voltage does not decrease in spite of the small size and of which the threshold voltage of the transistor can be adjusted by shape. The shape of a groove corner of the transistor as a semiconductor device is contained in a concentric circle having a radius of curvature r.+-.L/5 (L: channel length) and the radius of curvature r, i.e., the geometric parameter has a relationship with the doping concentration as shown in FIG. 1B. Alternatively, the average (a+b)/2 (geometric parameter) of the sum of the two sides opposite the right angle of a right triangle formed of a straight line in contact with the gate bottom in parallel to the substrate surface of a grooved gate transistor, a perpendicular line to the substrate bottom surface from the source and drain ends at a portion formed with a channel and a straight line in contact with the groove corner has a relationship with the doping concentration as shown in FIG. 1B. The threshold voltage is not reduced even when the channel length is decreased by adjusting the groove shape and the doping concentration.

摘要翻译： 尽管尺寸小，但是其晶体管的阈值电压可以通过形状来调整，其中阈值电压不降低的精细结构的开槽栅极晶体管。 作为半导体器件的晶体管的槽角的形状包含在具有曲率半径r +/- L / 5（L：沟道长度）和曲率半径r的同心圆中，即几何参数具有 与掺杂浓度的关系如图1所示。 1B。 或者，平行于沟槽的基板表面的与栅极底部接触的直线形成的直角三角形的直角相反的两侧的平均（a + b）/ 2（几何参数） 栅极晶体管，在形成有沟道的部分处的源极和漏极端部处的与衬底底表面的垂直线和与沟槽角接触的直线与图1所示的掺杂浓度具有关系。 1B。 即使通过调整沟槽形状和掺杂浓度来减小沟道长度，阈值电压也不会降低。

公开(公告)号：US4172260A

公开(公告)日：1979-10-23

申请号：US853548

申请日：1977-11-21

申请人： Takeaki Okabe ,  Isao Yoshida ,  Shikayuki Ochi ,  Hidefumi Itoh ,  Masatomo Furumi ,  Toru Toyabe ,  Mineo Katsueda ,  Yukio Shirota

发明人： Takeaki Okabe ,  Isao Yoshida ,  Shikayuki Ochi ,  Hidefumi Itoh ,  Masatomo Furumi ,  Toru Toyabe ,  Mineo Katsueda ,  Yukio Shirota

IPC分类号： H01L21/331 ,  H01L29/06 ,  H01L29/40 ,  H01L29/41 ,  H01L29/73 ,  H01L29/78

CPC分类号： H01L29/404 ,  H01L29/7835

摘要： In an insulated gate field effect transistor having a source region and a drain region of the P-conductivity type which are disposed in surface portions of a semiconductor substrate of the N-conductivity type in a manner to be spaced apart from each other, a gate electrode being disposed through an insulating film on the substrate between the source region and the drain region, an insulated gate field effect transistor wherein said drain region is disposed apart from said gate electrode, two regions of an intermediate region and a high resistance region which are of the P-conductivity type and which successively extend from said drain region towards the side of said gate electrode are disposed in surface portions of the substrate situated between said drain region and said gate electrode, said intermediate region having an impurity concentration lower than that of said drain region, said high resistance region having an impurity concentration lower than that of said intermediate region, and a source electrode extends over and beyond said gate electrode and said high resistance region through said insulating film and terminates over said intermediate region.

摘要翻译： 在绝缘栅场效应晶体管中，具有P导电类型的源区和漏区，它们以相互间隔开的方式设置在N-导电类型的半导体衬底的表面部分中，栅极 电极通过源极区域和漏极区域之间的衬底上的绝缘膜设置，绝缘栅极场效应晶体管，其中所述漏极区域与所述栅电极隔开，中间区域和高电阻区域的两个区域是 的P导电类型并且从所述漏极区域朝向所述栅电极的侧面依次延伸设置在位于所述漏极区域和所述栅电极之间的衬底的表面部分中，所述中间区域的杂质浓度低于 所述漏极区，所述高电阻区的杂质浓度低于所述中间区的杂质浓度 并且源电极通过所述绝缘膜延伸超过所述栅电极和所述高电阻区域，并且终止于所述中间区域上。