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    Touch screen panel and touch screen assembly including the same
    6.
    发明授权
    Touch screen panel and touch screen assembly including the same 有权
    触摸屏面板和触摸屏总成包括相同

    公开(公告)号：US09329625B2

    公开(公告)日：2016-05-03

    申请号：US13825496

    申请日：2011-07-16

    申请人： Hongchun Park ,  Hansoo Kim

    发明人： Hongchun Park ,  Hansoo Kim

    IPC分类号： G06F3/044 ,  G06F1/16 ,  G06F3/045 ,  H05K1/09 ,  G06F3/041

    CPC分类号： G06F3/0416 ,  G06F1/16 ,  G06F3/041 ,  G06F3/0412 ,  G06F3/044 ,  G06F3/045 ,  G06F2203/04103 ,  H01L2924/0002 ,  H05K1/03 ,  H05K1/09 ,  H05K1/092 ,  H05K1/111 ,  H05K2201/0145 ,  H05K2201/0154 ,  H01L2924/00

    摘要： The present invention relates to a touch screen panel and a touch screen assembly including the touch screen panel, the touch screen panel including a substrate; a transparent electrode layer formed on the substrate; a plurality of conductive wires electrically connected to the transparent electrode layer; an insulation film formed on the transparent electrode layer; and a plurality of conductive line, each of which is electrically connected to each of the plurality of conductive wires inside the insulation film, extended to an outside of the insulation film and exposed therefrom, whereby a PCB and conductive wires can be improved in electrical reliability.

    摘要翻译： 本发明涉及触摸屏面板和包括触摸屏面板的触摸屏组件，触摸屏面板包括基板; 形成在所述基板上的透明电极层; 电连接到透明电极层的多个导线; 形成在所述透明电极层上的绝缘膜; 以及多个导电线，每个导电线电连接到绝缘膜内部的多个导线中的每一个，延伸到绝缘膜的外部并暴露于绝缘膜的外部，从而可以提高PCB和导线的电可靠性 。

    Nonvolatile memory devices, read methods thereof and memory systems including the nonvolatile memory devices
    8.
    发明授权
    Nonvolatile memory devices, read methods thereof and memory systems including the nonvolatile memory devices 有权
    非易失性存储器件，其读取方法和包括非易失性存储器件的存储器系统

    公开(公告)号：US08913433B2

    公开(公告)日：2014-12-16

    申请号：US13093320

    申请日：2011-04-25

    申请人： Kihyun Kim ,  Hansoo Kim ,  Jaehoon Jang ,  Sunil Shim ,  Chulmin Park

    发明人： Kihyun Kim ,  Hansoo Kim ,  Jaehoon Jang ,  Sunil Shim ,  Chulmin Park

    IPC分类号： G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  H01L27/115 ,  G11C16/34

    CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3418 ,  H01L27/115 ,  H01L27/11582

    摘要： Reading methods of nonvolatile memory devices including a substrate and a plurality of memory cells which are stacked in a direction intersecting the substrate. The reading methods apply a bit line voltage to a plurality of bit lines and apply a first string selection line voltage to at least one selected string selection line. The reading methods apply a second string selection line voltage to at least one unselected string selection line and apply a read voltage to a plurality of word lines. The reading methods apply a first ground selection line voltage to at least one selected ground selection line and apply a second ground selection line voltage to at least one unselected ground selection line.

    摘要翻译： 非易失性存储器件的读取方法包括在与衬底交叉的方向上堆叠的衬底和多个存储单元。 读取方法将位线电压施加到多个位线，并将第一串选择线电压施加到至少一个所选择的串选择线。 读取方法将第二串选择线电压施加到至少一个未选择的串选择线，并将读电压施加到多个字线。 读取方法将第一接地选择线电压施加到至少一个所选择的接地选择线，并将第二接地选择线电压施加到至少一个未选择的接地选择线。

    Method of forming a three-dimensional semiconductor memory device comprising sub-cells, terraced structures and strapping regions
    10.
    发明授权
    Method of forming a three-dimensional semiconductor memory device comprising sub-cells, terraced structures and strapping regions 有权
    形成三维半导体存储器件的方法，其包括子单元，梯形结构和捆扎区域

    公开(公告)号：US08603906B2

    公开(公告)日：2013-12-10

    申请号：US13779334

    申请日：2013-02-27

    申请人： Sunil Shim ,  Sunghoi Hur ,  Hansoo Kim ,  Jaehoon Jang ,  Hoosung Cho

    发明人： Sunil Shim ,  Sunghoi Hur ,  Hansoo Kim ,  Jaehoon Jang ,  Hoosung Cho

    IPC分类号： H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L21/02365 ,  H01L21/02697 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

    摘要： Provided is a three-dimensional semiconductor memory device. The three-dimensional semiconductor memory device includes a substrate that has a cell array region including a pair of sub-cell regions and a strapping region interposed between the pair of sub-cell regions. A Plurality of sub-gates are sequentially stacked on the substrate in each of the sub-cell regions, and interconnections are electrically connected to extensions of the stacked sub-gates, respectively, which extend into the strapping region. Each of the interconnections is electrically connected to the extensions of the sub-gate which are disposed in the pair of the sub-cell regions, respectively, and which are located at the same level.

    摘要翻译： 提供一种三维半导体存储器件。 三维半导体存储器件包括具有包括一对子单元区域的单元阵列区域和插入该一对子单元区域之间的带状区域的基板。 多个子栅极依次层叠在每个子单元区域中的衬底上，并且互连电连接到延伸到捆扎区域中的堆叠子栅极的延伸部分。 每个互连电连接到分别设置在一对子单元区域中并且位于同一电平的子栅极的延伸部分。