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    Nonvolatile memory device and method for operating the same
    3.
    发明申请
    Nonvolatile memory device and method for operating the same 有权
    非易失性存储器件及其操作方法

    公开(公告)号：US20100172182A1

    公开(公告)日：2010-07-08

    申请号：US12654712

    申请日：2009-12-30

    申请人： Kwang-Soo Seol ,  Yoondong Park ,  Sukpil Kim

    发明人： Kwang-Soo Seol ,  Yoondong Park ,  Sukpil Kim

    IPC分类号： G11C16/04

    CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/3427 ,  G11C2213/71 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582

    摘要： Disclosed is a nonvolatile memory device which includes a plurality of cell array layers stacked on a semiconductor substrate. Each of the plurality of cell array layers includes a plurality of strings. Each of the plurality of strings has string and ground select transistors and a plurality of memory cells connected in series between the string and ground select transistors. A common source line is on each of the plurality of cell array layers. Each common source line is connected with first sides of the plurality of strings on a corresponding cell array layer. A plurality of bit lines is connected with second sides of the plurality of strings disposed on the cell array layers and arranged in the vertical direction to the semiconductor substrate. A plurality of word lines is connected with the plurality of memory cells.

    摘要翻译： 公开了一种非易失性存储器件，其包括堆叠在半导体衬底上的多个单元阵列层。 多个单元阵列层中的每一个包括多个串。 多个串中的每一个具有串和地选择晶体管以及串联连接在串和地选择晶体管之间的多个存储单元。 在多个单元阵列层中的每一个上都具有公共源极线。 每个公共源极线与相应的单元阵列层上的多个串的第一侧连接。 多个位线与布置在单元阵列层上的多个串的第二侧连接，并且在与半导体基板垂直的方向上布置。 多个字线与多个存储单元连接。

    Nonvolatile memory device and method for operating the same
    5.
    发明授权
    Nonvolatile memory device and method for operating the same 有权
    非易失性存储器件及其操作方法

    公开(公告)号：US08335109B2

    公开(公告)日：2012-12-18

    申请号：US12654712

    申请日：2009-12-30

    申请人： Kwang-Soo Seol ,  Yoondong Park ,  Sukpil Kim

    发明人： Kwang-Soo Seol ,  Yoondong Park ,  Sukpil Kim

    IPC分类号： G11C16/04

    CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/3427 ,  G11C2213/71 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582

    摘要： Disclosed is a nonvolatile memory device which includes a plurality of cell array layers stacked on a semiconductor substrate. Each of the plurality of cell array layers includes a plurality of strings. Each of the plurality of strings has string and ground select transistors and a plurality of memory cells connected in series between the string and ground select transistors. A common source line is on each of the plurality of cell array layers. Each common source line is connected with first sides of the plurality of strings on a corresponding cell array layer. A plurality of bit lines is connected with second sides of the plurality of strings disposed on the cell array layers and arranged in the vertical direction to the semiconductor substrate. A plurality of word lines is connected with the plurality of memory cells.

    摘要翻译： 公开了一种非易失性存储器件，其包括堆叠在半导体衬底上的多个单元阵列层。 多个单元阵列层中的每一个包括多个串。 多个串中的每一个具有串和地选择晶体管以及串联连接在串和地选择晶体管之间的多个存储单元。 在多个单元阵列层中的每一个上都具有公共源极线。 每个公共源极线与相应的单元阵列层上的多个串的第一侧连接。 多个位线与布置在单元阵列层上的多个串的第二侧连接，并且在与半导体基板垂直的方向上布置。 多个字线与多个存储单元连接。

    Methods of manufacturing vertical semiconductor devices
    6.
    发明授权
    Methods of manufacturing vertical semiconductor devices 有权
    制造垂直半导体器件的方法

    公开(公告)号：US08697524B2

    公开(公告)日：2014-04-15

    申请号：US13212485

    申请日：2011-08-18

    申请人： Byung-Kwan You ,  Kwang-Soo Seol ,  Young-Woo Park ,  Jin-Soo Lim

    发明人： Byung-Kwan You ,  Kwang-Soo Seol ,  Young-Woo Park ,  Jin-Soo Lim

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28282 ,  H01L21/02104 ,  H01L27/11582 ,  H01L29/7926

    摘要： Methods of manufacturing vertical semiconductor devices may include forming a mold structure including sacrificial layers and insulating interlayers with a first opening formed therethrough. The sacrificial layers and the insulating interlayers may be stacked repeatedly and alternately on a substrate. The first opening may expose the substrate. Blocking layers may be formed by oxidizing portions of the sacrificial layers exposed by the first opening. A first semiconductor layer pattern, a charge trapping layer pattern and a tunnel insulation layer pattern, respectively, may be formed on the sidewall of the first opening. A second semiconductor layer may be formed on the first polysilicon layer pattern and the bottom of the first opening. The sacrificial layers and the insulating interlayers may be partially removed to form a second opening. The sacrificial layers may be removed to form grooves between the insulating interlayers. Control gate electrodes may be formed in the grooves.

    摘要翻译： 制造垂直半导体器件的方法可以包括形成包括牺牲层和绝缘夹层的模具结构，其中形成有第一开口。 牺牲层和绝缘夹层可以重复地和交替地层叠在基板上。 第一开口可能暴露基板。 可以通过氧化由第一开口暴露的牺牲层的部分来形成阻挡层。 分别可以在第一开口的侧壁上形成第一半导体层图案，电荷俘获层图案和隧道绝缘层图案。 可以在第一多晶硅层图案和第一开口的底部上形成第二半导体层。 可以部分去除牺牲层和绝缘夹层以形成第二开口。 可以去除牺牲层以在绝缘夹层之间形成凹槽。 控制栅电极可以形成在凹槽中。

    Memory devices capable of reducing lateral movement of charges
    7.
    发明申请
    Memory devices capable of reducing lateral movement of charges 有权
    能够减少电荷横向移动的存储器件

    公开(公告)号：US20100044779A1

    公开(公告)日：2010-02-25

    申请号：US12461612

    申请日：2009-08-18

    申请人： Kwang-Soo Seol

    发明人： Kwang-Soo Seol

    IPC分类号： H01L29/792

    CPC分类号： H01L29/42344 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/4234 ,  H01L29/792

    摘要： Memory devices is provided, the memory devices include a tunneling insulating layer disposed on a substrate, a charge storage layer disposed on the tunneling insulating layer, a blocking insulating layer disposed on the charge storage layer and a control gate electrode disposed on the blocking insulating layer. The control gate electrode may have an edge portion spaced farther apart from the blocking insulating layer than a central portion of the control gate electrode to concentrate charge density distribution on a central portion of a memory cell.

    摘要翻译： 提供存储器件，存储器件包括设置在衬底上的隧道绝缘层，设置在隧道绝缘层上的电荷存储层，设置在电荷存储层上的阻挡绝缘层和设置在阻挡绝缘层上的控制栅电极 。 与控制栅极的中心部分相比，控制栅电极可以具有与阻挡绝缘层相距更远的边缘部分，以将电荷密度分布集中在存储器单元的中心部分上。

    Gate structure in non-volatile memory device
    10.
    发明授权
    Gate structure in non-volatile memory device 有权

    公开(公告)号：US08674429B2

    公开(公告)日：2014-03-18

    申请号：US13759195

    申请日：2013-02-05

    申请人： Jang-Gn Yun ,  Jung-Dal Choi ,  Kwang-Soo Seol

    发明人： Jang-Gn Yun ,  Jung-Dal Choi ,  Kwang-Soo Seol

    IPC分类号： H01L21/02

    CPC分类号： H01L29/7926 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792

    摘要： A gate structure of a non-volatile memory device and a method of forming the same including a tunnel oxide layer pattern, a charge trap layer pattern, a blocking dielectric layer pattern having the uppermost layer including a material having a first dielectric constant greater than that of a material included in the tunnel oxide layer pattern, and first and second conductive layer patterns. The gate structure includes a first spacer to cover at least the sidewall of the second conductive layer pattern. The gate structure includes a second spacer covering the sidewall of the first spacer and the sidewall of the first conductive layer pattern and including a material having a second dielectric constant equal to or greater than the first dielectric constant. In the non-volatile memory device including the gate structure, erase saturation caused by back tunneling is reduced.