公开(公告)号：US6057236A

公开(公告)日：2000-05-02

申请号：US105644

申请日：1998-06-26

申请人： Larry Clevenger ,  Mark Hoinkis ,  Roy C. Iggulden ,  Stefan J. Weber

发明人： Larry Clevenger ,  Mark Hoinkis ,  Roy C. Iggulden ,  Stefan J. Weber

IPC分类号： H01L21/3205 ,  C23C14/14 ,  C23C14/58 ,  C23C16/56 ,  C23C28/02 ,  H01L21/28 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/76868 ,  H01L21/76876 ,  H01L21/76882 ,  H01L23/5226 ,  H01L2924/0002

摘要： Improved methods for forming metal-filled structures in openings on substrates for integrated circuit devices are obtained by the formation of a discontinuous metal liner by CVD in an opening to be filled. The discontinuous metal liner surprisingly provides wetting equivalent to or better than continuous layer CVD liners. The CVD step is followed by depositing a further amount of metal by physical vapor deposition over the discontinuous layer in the opening, and reflowing the further amount of metal to obtain the metal-filled structure.The interior surface of the opening is preferably a conductive material such as titanium nitride. Preferably, the discontinuous metal layer is made of aluminum. The metal deposited by PVD is preferably aluminum or an aluminum alloy. The methods of the invention are especially useful for the filling of contact holes, damascene trenches and dual damascene trenches. The methods of the invention are especially useful for filling structures having an opening width less than 250 nm.

摘要翻译： 通过在待填充的开口中通过CVD形成不连续的金属衬垫来获得用于在集成电路器件的衬底上的开口中形成金属填充结构的改进方法。 不连续的金属衬垫令人惊讶地提供了与连续层CVD衬垫相当或更好的润湿。 CVD步骤之后，通过在开口中的不连续层上的物理气相沉积沉积更多量的金属，再回流另外的金属以获得填充金属的结构。 开口的内表面优选为诸如氮化钛的导电材料。 优选地，不连续金属层由铝制成。 通过PVD沉积的金属优选为铝或铝合金。 本发明的方法对于填充接触孔，镶嵌沟槽和双镶嵌沟槽特别有用。 本发明的方法对于填充具有小于250nm的开口宽度的结构特别有用。

公开(公告)号：US06870263B1

公开(公告)日：2005-03-22

申请号：US09052688

申请日：1998-03-31

申请人： Lawrence A. Clevenger ,  Ronald G. Filippi ,  Mark Hoinkis ,  Jeffery L. Hurd ,  Roy C. Iggulden ,  Herbert Palm ,  Hans W. Poetzlberger ,  Kenneth P. Rodbell ,  Florian Schnabel ,  Stefan Weber ,  Ebrahim A. Mehter

发明人： Lawrence A. Clevenger ,  Ronald G. Filippi ,  Mark Hoinkis ,  Jeffery L. Hurd ,  Roy C. Iggulden ,  Herbert Palm ,  Hans W. Poetzlberger ,  Kenneth P. Rodbell ,  Florian Schnabel ,  Stefan Weber ,  Ebrahim A. Mehter

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  H01L23/48

CPC分类号： H01L21/76843 ,  H01L21/76807 ,  H01L21/76849 ,  H01L21/76876 ,  H01L23/485 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A conductor for interconnecting integrated circuit components having improved reliability. The conductor includes a liner surrounding at least three surfaces of the conductor, producing a low textured conductor. It has been found that low textured conductor results in improved electromigration lifetime.

摘要翻译： 用于互连具有改进的可靠性的集成电路部件的导体。 导体包括围绕导体的至少三个表面的衬垫，产生低纹理导体。 已经发现，低纹理导体导致改善的电迁移寿命。

公开(公告)号：US06242789B1

公开(公告)日：2001-06-05

申请号：US09255767

申请日：1999-02-23

申请人： Stefan J. Weber ,  Axel Christoph Brintzinger ,  Roy Iggulden ,  Mark Hoinkis ,  Chandrasekhar Narayan ,  Robert Van Den Berg

发明人： Stefan J. Weber ,  Axel Christoph Brintzinger ,  Roy Iggulden ,  Mark Hoinkis ,  Chandrasekhar Narayan ,  Robert Van Den Berg

IPC分类号： H01L2900

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fuse for semiconductor devices in accordance with the present invention includes a substrate having a conductive path disposed on a surface thereof, a dielectric layer disposed on the substrate and a vertical fuse disposed perpendicularly to the surface through the dielectric layer and connecting to the conductive path, the vertical fuse forming a cavity having a liner material disposed along vertical surfaces of the cavity, the vertical surfaces being melted to blow the fuse. Methods for fabrication of the vertical fuse are also included.

摘要翻译： 根据本发明的用于半导体器件的熔丝包括：具有设置在其表面上的导电通路的基板，设置在基板上的电介质层和垂直于通过介电层垂直于表面设置并连接到导电路径的熔丝 垂直熔丝形成具有沿着空腔的垂直表面设置的衬垫材料的空腔，垂直表面被熔化以熔断熔断器。 还包括制造垂直保险丝的方法。

公开(公告)号：US07241696B2

公开(公告)日：2007-07-10

申请号：US10318606

申请日：2002-12-11

申请人： Larry Clevenger ,  Timothy Joseph Dalton ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Kaushik Kumar ,  Douglas C. La Tulipe, Jr. ,  Soon-Cheon Seo ,  Andrew Herbert Simon ,  Yun-Yu Wang ,  Chih-Chao Yang ,  Haining Yang

发明人： Larry Clevenger ,  Timothy Joseph Dalton ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Kaushik Kumar ,  Douglas C. La Tulipe, Jr. ,  Soon-Cheon Seo ,  Andrew Herbert Simon ,  Yun-Yu Wang ,  Chih-Chao Yang ,  Haining Yang

IPC分类号： H01L21/00

CPC分类号： H01L21/76843 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76865

摘要： Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor. In the process of sputter etching, the capping layer is redeposited onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.

摘要翻译： 公开了一种用于在半导体晶片的互连结构上沉积金属层的方法。 在该方法中，金属导体被覆盖层和电介质层覆盖。 对电介质层进行图案化以使覆盖层露出。 然后溅射蚀刻覆盖层以去除覆盖层并暴露金属导体。 在溅射蚀刻的过程中，覆盖层被再沉积到图案的侧壁上。 最后，至少一层沉积到图案中并覆盖再沉积的覆盖层。

公开(公告)号：US20050077628A1

公开(公告)日：2005-04-14

申请号：US10684952

申请日：2003-10-14

申请人： Kaushik Kumar ,  Timothy Dalton ,  Larry Clevenger ,  Andy Cowley ,  Douglas La Tulipe ,  Mark Hoinkis ,  Chih-Chao Yang ,  Yi-Hsiung Lin ,  Erdem Kaltalioglu ,  Markus Naujok ,  Jochen Schacht

发明人： Kaushik Kumar ,  Timothy Dalton ,  Larry Clevenger ,  Andy Cowley ,  Douglas La Tulipe ,  Mark Hoinkis ,  Chih-Chao Yang ,  Yi-Hsiung Lin ,  Erdem Kaltalioglu ,  Markus Naujok ,  Jochen Schacht

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/48

CPC分类号： H01L21/76835 ,  H01L21/76811 ,  H01L21/76813 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A dual damascene structure and method of fabrication thereof. An insulating layer comprises a first dielectric material and a second dielectric material, the second dielectric material being different from the first dielectric material. First conductive regions having a first pattern are formed in the first dielectric material, and second conductive regions having a second pattern are formed in the second dielectric material, the second pattern being different from the first pattern. One of the first dielectric material and the second dielectric material comprises an organic material, and the other dielectric material comprises an inorganic material. One of the first and second dielectric materials is etchable selective to the other dielectric material. A method of cleaning a semiconductor wafer processing chamber while a wafer remains residing within the chamber is also disclosed.

公开(公告)号：US07091612B2

公开(公告)日：2006-08-15

申请号：US10684952

申请日：2003-10-14

申请人： Kaushik Kumar ,  Timothy Dalton ,  Larry Clevenger ,  Andy Cowley ,  Douglas C. La Tulipe ,  Mark Hoinkis ,  Chih-Chao Yang ,  Yi-Hsiung Lin ,  Erdem Kaltalioglu ,  Markus Naujok ,  Jochen Schacht

发明人： Kaushik Kumar ,  Timothy Dalton ,  Larry Clevenger ,  Andy Cowley ,  Douglas C. La Tulipe ,  Mark Hoinkis ,  Chih-Chao Yang ,  Yi-Hsiung Lin ,  Erdem Kaltalioglu ,  Markus Naujok ,  Jochen Schacht

IPC分类号： H01L23/12 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L21/76835 ,  H01L21/76811 ,  H01L21/76813 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A dual damascene structure and method of fabrication thereof. An insulating layer comprises a first dielectric material and a second dielectric material, the second dielectric material being different from the first dielectric material. First conductive regions having a first pattern are formed in the first dielectric material, and second conductive regions having a second pattern are formed in the second dielectric material, the second pattern being different from the first pattern. One of the first dielectric material and the second dielectric material comprises an organic material, and the other dielectric material comprises an inorganic material. One of the first and second dielectric materials is etchable selective to the other dielectric material. A method of cleaning a semiconductor wafer processing chamber while a wafer remains residing within the chamber is also disclosed.

公开(公告)号：US20050208742A1

公开(公告)日：2005-09-22

申请号：US10708648

申请日：2004-03-17

申请人： William America ,  Larry Clevenger ,  Andy Cowley ,  Timothy Dalton ,  Mark Hoinkis ,  Kaushik Kumar ,  Douglas La Tulipe

发明人： William America ,  Larry Clevenger ,  Andy Cowley ,  Timothy Dalton ,  Mark Hoinkis ,  Kaushik Kumar ,  Douglas La Tulipe

IPC分类号： H01L21/033 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/76811 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76834

摘要： A method of producing an oxidized tantalum nitride (TaOxNx) hardmask layer for use in dual-damascene processing is described. Fine-line dual-damascene processing places competing, conflicting demands on the hardmask. Whereas critical dimension control needs a thicker hardmask, optical lithographic alignment is frustrated by the opacity of thick tantalum nitride (TaN). The technique solves the problem of TaN hardmask opacity with increasing thickness by oxidizing the TaN layer. Oxidation of the TaN hardmask increases the thickness of the hardmask to two to four times its original thickness and simultaneously increases its transparency by greater than ten times. This permits better CD control associated with a thicker hardmask while facilitating optical lithographic alignment.

摘要翻译： 描述了用于双镶嵌加工的氧化氮化钽（TaO x N N N x S）硬掩模层的制造方法。 精细的双镶嵌加工对硬掩模产生了竞争，冲突的要求。 尽管临界尺寸控制需要较厚的硬掩模，但由于厚氮化钽（TaN）的不透明度，光学平版印刷对挫败感到沮丧。 该技术通过氧化TaN层来解决厚度增加的TaN硬掩模不透明度问题。 TaN硬掩模的氧化将硬掩模的厚度增加到其原始厚度的两到四倍，同时将其透明度提高了十倍以上。 这允许与更厚的硬掩模相关联的更好的CD控制，同时促进光学光刻对准。

公开(公告)号：US06218279B1

公开(公告)日：2001-04-17

申请号：US09512648

申请日：2000-02-24

申请人： Stefan J. Weber ,  Axel Christoph Brintzinger ,  Roy Iggulden ,  Mark Hoinkis ,  Chandrasekhar Narayan ,  Robert Van den Berg

发明人： Stefan J. Weber ,  Axel Christoph Brintzinger ,  Roy Iggulden ,  Mark Hoinkis ,  Chandrasekhar Narayan ,  Robert Van den Berg

IPC分类号： H01L2144

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fuse for semiconductor devices in accordance with the present invention includes a substrate having a conductive path disposed on a surface thereof, a dielectric layer disposed on the substrate and a vertical fuse disposed perpendicularly to the surface through the dielectric layer and connecting to the conductive path, the vertical fuse forming a cavity having a liner material disposed along vertical surfaces of the cavity, the vertical surfaces being melted to blow the fuse. Methods for fabrication of the vertical fuse are also included.

公开(公告)号：US07368804B2

公开(公告)日：2008-05-06

申请号：US10439874

申请日：2003-05-16

申请人： Mark Hoinkis ,  Matthias Hierlemann ,  Gerald Friese ,  Andy Cowley ,  Dennis J. Warner ,  Erdem Kaltalioglu

发明人： Mark Hoinkis ,  Matthias Hierlemann ,  Gerald Friese ,  Andy Cowley ,  Dennis J. Warner ,  Erdem Kaltalioglu

IPC分类号： H01L23/58 ,  H01L23/48

CPC分类号： H01L23/5226 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer.

摘要翻译： 提供了一种方法，装置和系统，用于在通孔下方的线宽大于基准规则时，减少半导体结构的通孔结构中的应力，包括提供至少与基底层一样大的通孔， 通孔，提供通孔条来代替通孔，将通孔下方的金属线宽开槽，或者提供具有侧壁间隔物的超尺寸通孔。

公开(公告)号：US07052621B2

公开(公告)日：2006-05-30

申请号：US10461090

申请日：2003-06-13

申请人： Kaushik Kumar ,  Lawrence Clevenger ,  Timothy Dalton ,  Douglas C. La Tulipe ,  Andy Cowley ,  Erdem Kaltalioglu ,  Jochen Schacht ,  Andrew H. Simon ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Chih-Chao Yang

发明人： Kaushik Kumar ,  Lawrence Clevenger ,  Timothy Dalton ,  Douglas C. La Tulipe ,  Andy Cowley ,  Erdem Kaltalioglu ,  Jochen Schacht ,  Andrew H. Simon ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Chih-Chao Yang

IPC分类号： C23F1/00

CPC分类号： H01L21/76832 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76813 ,  H01L2221/1036 ,  Y10T428/12576 ,  Y10T428/12806 ,  Y10T428/265 ,  Y10T428/31678

摘要： A metal hardmask for use with a Dual Damascene process used in the manufacturing of semiconductor devices. The metal hardmask has advantageous translucent characteristics to facilitate alignment between levels while fabricating a semiconductor device and avoids the formation of metal oxide residue deposits. The metal hardmask comprises a first or primary layer of TiN (titanium nitride) and a second or capping layer of TaN (tantalum nitride).

摘要翻译： 用于制造半导体器件的双镶嵌工艺的金属硬掩模。 金属硬掩模具有有利的半透明特性，以有助于在制造半导体器件时水平之间的对准，并避免形成金属氧化物残留物沉积物。 金属硬掩模包括TiN（氮化钛）的第一或第一层和TaN（氮化钽）的第二或覆盖层。