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公开(公告)号：US20120171877A1
公开(公告)日：2012-07-05
申请号：US13323902
申请日：2011-12-13
CPC分类号： H01L21/76898 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/0501 , H01L2224/0502 , H01L2224/05099 , H01L2224/05548 , H01L2224/05552 , H01L2224/05556 , H01L2224/0556 , H01L2224/05571 , H01L2224/05599 , H01L2224/1147 , H01L2224/13111 , H01L2224/13147 , H01L2224/13565 , H01L2224/1357 , H01L2224/13657 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01058 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , Y10T29/49117 , H01L2924/01015 , H01L2924/00012 , H01L2924/00
摘要： An electrical connection structure for an integrated circuit chip includes a through via provided in a opening and a laterally adjacent void that are formed in a rear face of a substrate die. A front face of the substrate die includes integrated circuits and a layer incorporating a front electrical interconnect network. The via extends through the substrate die to reach a connection portion of the front electrical interconnect network. An electrical connection pillar made of an electrically conductive material is formed on a rear part of the electrical connection via above the void. A local external protection layer may at least partly cover the electrical connection via and the electrical connection pillar.
摘要翻译： 用于集成电路芯片的电连接结构包括设置在开口中的通孔和形成在衬底管芯的后表面中的横向相邻的空隙。 衬底管芯的前表面包括集成电路和包含前部电互连网络的层。 通孔延伸穿过衬底管芯以到达前电互连网络的连接部分。 由导电材料制成的电连接柱通过空隙上方形成在电连接的后部。 局部外部保护层可以至少部分地覆盖电连接柱和电连接柱。
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公开(公告)号：US20120153425A1
公开(公告)日：2012-06-21
申请号：US13315441
申请日：2011-12-09
CPC分类号： H01L21/78
摘要： Integrated-circuit chips are fabricated according to a process wherein weak portions are formed in a substrate wafer surrounding a plurality of locations. An integrated-circuit chip is defined at each location by destroying the weak portions so as to singulate integrated-circuit chips.
摘要翻译： 集成电路芯片是根据其中在围绕多个位置的衬底晶片中形成弱部分的工艺制造的。 在每个位置通过破坏弱部分来限定集成电路芯片，以便对集成电路芯片进行分离。
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3.发明授权公开(公告)号：US08674517B2
公开(公告)日：2014-03-18
申请号：US13328175
申请日：2011-12-16
IPC分类号： H01L23/488 , H01L21/50
CPC分类号： H01L24/16 , H01L23/481 , H01L24/13 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L25/50 , H01L2224/02311 , H01L2224/02331 , H01L2224/02372 , H01L2224/0239 , H01L2224/03462 , H01L2224/0401 , H01L2224/05568 , H01L2224/05573 , H01L2224/05647 , H01L2224/13024 , H01L2224/13099 , H01L2224/13199 , H01L2224/13311 , H01L2224/13347 , H01L2224/16145 , H01L2224/16147 , H01L2224/16225 , H01L2224/16237 , H01L2224/32145 , H01L2224/32225 , H01L2224/73104 , H01L2224/73204 , H01L2224/81141 , H01L2224/81191 , H01L2224/81801 , H01L2224/83862 , H01L2224/9211 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01058 , H01L2924/01073 , H01L2924/014 , H01L2924/14 , H01L2224/81 , H01L2224/83 , H01L2224/05099 , H01L2924/00 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599 , H01L2224/05552
摘要： A semiconductor device includes an assembly of two integrated circuits. The assembly has a layer of photoresist filling the space between the two integrated circuits, and at least one electrically conducting pillar within the resist and electrically coupling the two integrated circuits.
摘要翻译： 半导体器件包括两个集成电路的组件。 组件具有填充两个集成电路之间的空间的光致抗蚀剂层，以及抗蚀剂内的至少一个导电柱，并电耦合两个集成电路。
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公开(公告)号：US08673740B2
公开(公告)日：2014-03-18
申请号：US13616288
申请日：2012-09-14
IPC分类号： H01L21/762 , H01L21/66
CPC分类号： H01L21/76898 , H01L21/6835 , H01L24/11 , H01L24/13 , H01L24/81 , H01L24/94 , H01L25/0657 , H01L2221/68318 , H01L2221/68327 , H01L2221/6834 , H01L2221/68381 , H01L2224/02372 , H01L2224/0401 , H01L2224/05008 , H01L2224/05548 , H01L2224/05569 , H01L2224/11462 , H01L2224/1147 , H01L2224/13009 , H01L2224/13022 , H01L2224/13024 , H01L2224/13082 , H01L2224/13111 , H01L2224/13147 , H01L2224/16148 , H01L2224/17181 , H01L2224/81005 , H01L2224/81193 , H01L2224/81815 , H01L2224/9202 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2924/01322 , H01L2924/00014 , H01L2924/01047 , H01L2924/01029 , H01L2224/81 , H01L2224/11 , H01L2224/03 , H01L2924/00
摘要： A method is for formation of an electrically conducting through-via within a first semiconductor support having a front face and comprising a silicon substrate. The method may include forming of a first insulating layer on top of the front face of the first semiconductor support, fabricating a handle including, within an additional rigid semiconductor support having an intermediate semiconductor layer, and forming on either side of the intermediate semiconductor layer of a porous region and of an additional insulating layer. The method may also include direct bonding of the first insulating layer and of the additional insulating layer, and thinning of the silicon substrate of the first semiconductor support so as to form a back face opposite to the front face.
摘要翻译： 一种用于在具有正面并且包括硅衬底的第一半导体衬底内形成导电通孔的方法。 该方法可以包括在第一半导体支撑件的前表面的顶部上形成第一绝缘层，制造把手包括在具有中间半导体层的另外的刚性半导体支架内，并在中间半导体层的中间半导体层的任一侧上形成 多孔区域和附加绝缘层。 该方法还可以包括直接接合第一绝缘层和附加绝缘层，以及使第一半导体支撑件的硅衬底变薄，从而形成与正面相对的背面。
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公开(公告)号：US09293429B2
公开(公告)日：2016-03-22
申请号：US13554831
申请日：2012-07-20
申请人： Laurent-Luc Chapelon
发明人： Laurent-Luc Chapelon
IPC分类号： H01L23/48 , H01L23/00 , H01L21/683 , H01L23/31
CPC分类号： H01L24/05 , H01L21/6835 , H01L23/3192 , H01L23/481 , H01L24/03 , H01L24/11 , H01L24/13 , H01L2221/68381 , H01L2224/0401 , H01L2224/1147 , H01L2224/11849 , H01L2224/1301 , H01L2224/13022 , H01L2224/13147 , H01L2924/01029 , H01L2924/15311
摘要： An electronic chip including a semiconductor substrate (1) covered with an insulating layer (4) including metal interconnection levels (3) and interconnection pillars (10) connected to said metal interconnection levels (3), said pillars (110) forming regions (111) protruding from the upper surface of said insulating layer (4) and capable of forming an electric contact, wherein said pillars (110) have a built-in portion (115) in a housing formed across the thickness of at least said insulating layer (4).
摘要翻译： 一种电子芯片，其包括覆盖有绝缘层（4）的半导体衬底（1），所述绝缘层包括连接到所述金属互连层（3）的金属互连层（3）和互连柱（10），所述柱（110）形成区域 ）从所述绝缘层（4）的上表面突出并且能够形成电接触，其中所述支柱（110）在形成在至少所述绝缘层的厚度上的壳体中具有内置部分（115） 4）。
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公开(公告)号：US08466038B2
公开(公告)日：2013-06-18
申请号：US13315456
申请日：2011-12-09
CPC分类号： H01L21/6835 , H01L21/76898
摘要： Front-side integrated parts of integrated-circuit chips are produced at locations on a substrate wafer. The front-side parts have a front side. A support wafer having a bearing side is mounted with the bearing side on top of said front-side parts. The support wafer includes at least one weak surface layer. This weak surface layer is attached to the substrate wafer using a retaining adhesive. In one implementation, the weak surface layer is attached to a front surface of the wafer. In another implementation, the weak surface layer is attached to a peripheral edge of the wafer. After attaching the support wafer, back-side integrated parts of the integrated-circuit chips are produced on the substrate wafer. The weak surface layer is then destroyed so as to demount the support wafer from the substrate wafer.
摘要翻译： 集成电路芯片的前端集成部件在基板晶圆上的位置产生。 前侧部件具有前侧。 具有轴承侧的支撑晶片将轴承侧安装在所述前侧部分的顶部。 支撑晶片包括至少一个弱表面层。 该弱表面层使用保持粘合剂附接到基底晶片。 在一个实施方案中，弱表面层附着到晶片的前表面。 在另一个实施方案中，弱表面层附着到晶片的周边边缘。 在安装支撑晶片之后，在基板晶片上制造集成电路芯片的背面集成部件。 然后破坏弱表面层，从而从支撑晶片脱离衬底晶片。
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7.发明申请METHOD FOR DETERMINING THE LOCAL STRESS INDUCED IN A SEMICONDUCTOR MATERIAL WAFER BY THROUGH VIAS 有权通过VIAS测定半导体材料中的局部应力的方法公开(公告)号：US20130112974A1
公开(公告)日：2013-05-09
申请号：US13524699
申请日：2012-06-15
IPC分类号： H01L21/66
CPC分类号： H01L22/12 , H01L22/20 , H01L22/30 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A method for determining, in a first semiconductor material wafer having at least one through via, mechanical stress induced by the at least one through via, this method including the steps of: manufacturing a test structure from a second wafer of the same nature as the first wafer, in which the at least one through via is formed by a substantially identical method, a rear surface layer being further arranged on this second wafer so that the via emerges on the layer; measuring the mechanical stress in the rear surface layer; and deducing therefrom the mechanical stress induced in the first semiconductor material wafer.
摘要翻译： 一种用于在具有由所述至少一个通孔引起的至少一个通孔机械应力的第一半导体材料晶片中确定该方法，所述方法包括以下步骤：从与所述至少一个通孔相同性质的第二晶片制造测试结构， 第一晶片，其中通过基本相同的方法形成所述至少一个通孔，在所述第二晶片上进一步布置后表面层，使得所述通孔出现在所述层上; 测量后表面层的机械应力; 并从中推导出在第一半导体材料晶片中引起的机械应力。
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公开(公告)号：US20120156859A1
公开(公告)日：2012-06-21
申请号：US13315456
申请日：2011-12-09
IPC分类号： H01L21/302
CPC分类号： H01L21/6835 , H01L21/76898
摘要： Front-side integrated parts of integrated-circuit chips are produced at locations on a substrate wafer. The front-side parts have a front side. A support wafer having a bearing side is mounted with the bearing side on top of said front-side parts. The support wafer includes at least one weak surface layer. This weak surface layer is attached to the substrate wafer using a retaining adhesive. In one implementation, the weak surface layer is attached to a front surface of the wafer. In another implementation, the weak surface layer is attached to a peripheral edge of the wafer. After attaching the support wafer, back-side integrated parts of the integrated-circuit chips are produced on the substrate wafer. The weak surface layer is then destroyed so as to demount the support wafer from the substrate wafer.
摘要翻译： 集成电路芯片的前端集成部件在基板晶圆上的位置产生。 前侧部件具有前侧。 具有轴承侧的支撑晶片将轴承侧安装在所述前侧部分的顶部。 支撑晶片包括至少一个弱表面层。 该弱表面层使用保持粘合剂附接到基底晶片。 在一个实施方案中，弱表面层附着到晶片的前表面。 在另一个实施方案中，弱表面层附着到晶片的周边边缘。 在安装支撑晶片之后，在基板晶片上制造集成电路芯片的背面集成部件。 然后破坏弱表面层，从而从支撑晶片脱离衬底晶片。
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公开(公告)号：US08980738B2
公开(公告)日：2015-03-17
申请号：US13323902
申请日：2011-12-13
CPC分类号： H01L21/76898 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/0501 , H01L2224/0502 , H01L2224/05099 , H01L2224/05548 , H01L2224/05552 , H01L2224/05556 , H01L2224/0556 , H01L2224/05571 , H01L2224/05599 , H01L2224/1147 , H01L2224/13111 , H01L2224/13147 , H01L2224/13565 , H01L2224/1357 , H01L2224/13657 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01058 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , Y10T29/49117 , H01L2924/01015 , H01L2924/00012 , H01L2924/00
摘要： An electrical connection structure for an integrated circuit chip includes a through via provided in a opening and a laterally adjacent void that are formed in a rear face of a substrate die. A front face of the substrate die includes integrated circuits and a layer incorporating a front electrical interconnect network. The via extends through the substrate die to reach a connection portion of the front electrical interconnect network. An electrical connection pillar made of an electrically conductive material is formed on a rear part of the electrical connection via above the void. A local external protection layer may at least partly cover the electrical connection via and the electrical connection pillar.
摘要翻译： 用于集成电路芯片的电连接结构包括设置在开口中的通孔和形成在衬底管芯的后表面中的横向相邻的空隙。 衬底管芯的前表面包括集成电路和包含前部电互连网络的层。 通孔延伸穿过衬底管芯以到达前电互连网络的连接部分。 由导电材料制成的电连接柱通过空隙上方形成在电连接的后部。 局部外部保护层可以至少部分地覆盖电连接柱和电连接柱。
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10.发明授权Method for determining the local stress induced in a semiconductor material wafer by through vias 有权用于通过通孔确定在半导体材料晶片中引起的局部应力的方法公开(公告)号：US08726736B2
公开(公告)日：2014-05-20
申请号：US13524699
申请日：2012-06-15
IPC分类号： G01B5/00
CPC分类号： H01L22/12 , H01L22/20 , H01L22/30 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A method for determining, in a first semiconductor material wafer having at least one through via, mechanical stress induced by the at least one through via, this method including the steps of: manufacturing a test structure from a second wafer of the same nature as the first wafer, in which the at least one through via is formed by a substantially identical method, a rear surface layer being further arranged on this second wafer so that the via emerges on the layer; measuring the mechanical stress in the rear surface layer; and deducing therefrom the mechanical stress induced in the first semiconductor material wafer.
摘要翻译： 一种用于在具有由所述至少一个通孔引起的至少一个通孔机械应力的第一半导体材料晶片中确定该方法，所述方法包括以下步骤：从与所述至少一个通孔相同性质的第二晶片制造测试结构， 第一晶片，其中通过基本相同的方法形成所述至少一个通孔，在所述第二晶片上进一步布置后表面层，使得所述通孔出现在所述层上; 测量后表面层的机械应力; 并从中推导出在第一半导体材料晶片中引起的机械应力。
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