公开(公告)号：US20110067629A1

公开(公告)日：2011-03-24

申请号：US12957104

申请日：2010-11-30

申请人： M. Noel Rocklein ,  F. Daniel Gealy

发明人： M. Noel Rocklein ,  F. Daniel Gealy

IPC分类号： C23C16/455

CPC分类号： H01L21/28562 ,  C23C16/405 ,  C23C16/44 ,  C23C16/45525 ,  H01L21/28556 ,  H01L21/76843 ,  H01L21/76877 ,  H01L28/91

摘要： Methods and devices for controlling a growth rate of films in semiconductor structures are shown. Chemical vapor deposition methods and devices include the use of a reaction inhibitor that selectively varies a deposition rate along a surface. One specific method includes atomic layer deposition. One method shown provides high step coverage over features such as trenches in trench plate capacitors. Also shown are methods and devices to provide uniform batch reactor layer thicknesses. Also shown are methods for forming alloy layers with high control over composition. Also shown are methods to selectively control growth rate to provide growth only on selected surfaces.

摘要翻译： 示出了用于控制半导体结构中的膜的生长速率的方法和装置。 化学气相沉积方法和装置包括使用选择性地改变沿着表面的沉积速率的反应抑制剂。 一种具体方法包括原子层沉积。 所示的一种方法提供了诸如沟槽板电容器中的沟槽的特征的高阶覆盖。 还示出了提供均匀间歇反应堆层厚度的方法和装置。 还示出了用于形成具有高组成控制的合金层的方法。 还示出了选择性地控制生长速率以仅在所选表面上提供生长的方法。

公开(公告)号：US07863198B2

公开(公告)日：2011-01-04

申请号：US11419173

申请日：2006-05-18

申请人： M. Noel Rocklein ,  F. Daniel Gealy

发明人： M. Noel Rocklein ,  F. Daniel Gealy

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/28562 ,  C23C16/405 ,  C23C16/44 ,  C23C16/45525 ,  H01L21/28556 ,  H01L21/76843 ,  H01L21/76877 ,  H01L28/91

摘要： Methods and devices for controlling a growth rate of films in semiconductor structures are shown. Chemical vapor deposition methods and devices include the use of a reaction inhibitor that selectively varies a deposition rate along a surface. One specific method includes atomic layer deposition. One method shown provides high step coverage over features such as trenches in trench plate capacitors. Also shown are methods and devices to provide uniform batch reactor layer thicknesses. Also shown are methods for forming alloy layers with high control over composition. Also shown are methods to selectively control growth rate to provide growth only on selected surfaces.

摘要翻译： 示出了用于控制半导体结构中的膜的生长速率的方法和装置。 化学气相沉积方法和装置包括使用选择性地改变沿着表面的沉积速率的反应抑制剂。 一种具体方法包括原子层沉积。 所示的一种方法提供了诸如沟槽板电容器中的沟槽的特征的高阶覆盖。 还示出了提供均匀间歇反应堆层厚度的方法和装置。 还示出了用于形成具有高组成控制的合金层的方法。 还示出了选择性地控制生长速率以仅在所选表面上提供生长的方法。

公开(公告)号：US20070269982A1

公开(公告)日：2007-11-22

申请号：US11419173

申请日：2006-05-18

申请人： M. Noel Rocklein ,  F. Daniel Gealy

发明人： M. Noel Rocklein ,  F. Daniel Gealy

IPC分类号： H01L21/44 ,  H01L21/76 ,  B05D3/00

CPC分类号： H01L21/28562 ,  C23C16/405 ,  C23C16/44 ,  C23C16/45525 ,  H01L21/28556 ,  H01L21/76843 ,  H01L21/76877 ,  H01L28/91

摘要： Methods and devices for controlling a growth rate of films in semiconductor structures are shown. Chemical vapor deposition methods and devices include the use of a reaction inhibitor that selectively varies a deposition rate along a surface. One specific method includes atomic layer deposition. One method shown provides high step coverage over features such as trenches in trench plate capacitors. Also shown are methods and devices to provide uniform batch reactor layer thicknesses. Also shown are methods for forming alloy layers with high control over composition. Also shown are methods to selectively control growth rate to provide growth only on selected surfaces.

摘要翻译： 示出了用于控制半导体结构中的膜的生长速率的方法和装置。 化学气相沉积方法和装置包括使用选择性地改变沿着表面的沉积速率的反应抑制剂。 一种具体方法包括原子层沉积。 所示的一种方法提供了诸如沟槽板电容器中的沟槽的特征的高阶覆盖。 还示出了提供均匀间歇反应堆层厚度的方法和装置。 还示出了用于形成具有高组成控制的合金层的方法。 还示出了选择性地控制生长速率以仅在所选表面上提供生长的方法。

公开(公告)号：US08691656B2

公开(公告)日：2014-04-08

申请号：US13226787

申请日：2011-09-07

申请人： Brett W. Busch ,  David K. Hwang ,  F. Daniel Gealy

发明人： Brett W. Busch ,  David K. Hwang ,  F. Daniel Gealy

IPC分类号： H01L21/8242

CPC分类号： H01L21/76879 ,  B82Y10/00 ,  H01L21/28525 ,  H01L21/76885 ,  H01L21/76897 ,  H01L27/10811 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10888 ,  H01L28/91 ,  Y10S977/773

摘要： The invention includes methods of electrically interconnecting different elevation conductive structures, methods of forming capacitors, methods of forming an interconnect between a substrate bit line contact and a bit line in DRAM, and methods of forming DRAM memory cells. In one implementation, a method of electrically interconnecting different elevation conductive structures includes forming a first conductive structure comprising a first electrically conductive surface at a first elevation of a substrate. A nanowhisker is grown from the first electrically conductive surface, and is provided to be electrically conductive. Electrically insulative material is provided about the nanowhisker. An electrically conductive material is deposited over the electrically insulative material in electrical contact with the nanowhisker at a second elevation which is elevationally outward of the first elevation, and the electrically conductive material is provided into a second conductive structure. Other aspects and implementations are contemplated.

摘要翻译： 本发明包括电互连不同高程导电结构的方法，形成电容器的方法，在DRAM中形成衬底位线接触和位线之间的互连的方法，以及形成DRAM存储单元的方法。 在一个实施方式中，电连接不同高程导电结构的方法包括在衬底的第一高度处形成包括第一导电表面的第一导电结构。 纳米晶须从第一导电表面生长，并被提供为导电的。 提供关于纳米晶须的电绝缘材料。 导电材料沉积在电绝缘材料上，在第二高度处与纳米晶须电接触，第二高度位于第一高度的正上方，并且导电材料被提供到第二导电结构中。 考虑了其他方面和实现。

公开(公告)号：US20110318921A1

公开(公告)日：2011-12-29

申请号：US13226787

申请日：2011-09-07

申请人： Brett W. Busch ,  David K. Hwang ,  F. Daniel Gealy

发明人： Brett W. Busch ,  David K. Hwang ,  F. Daniel Gealy

IPC分类号： H01L21/28 ,  B82Y40/00

CPC分类号： H01L21/76879 ,  B82Y10/00 ,  H01L21/28525 ,  H01L21/76885 ,  H01L21/76897 ,  H01L27/10811 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10888 ,  H01L28/91 ,  Y10S977/773

摘要： The invention includes methods of electrically interconnecting different elevation conductive structures, methods of forming capacitors, methods of forming an interconnect between a substrate bit line contact and a bit line in DRAM, and methods of forming DRAM memory cells. In one implementation, a method of electrically interconnecting different elevation conductive structures includes forming a first conductive structure comprising a first electrically conductive surface at a first elevation of a substrate. A nanowhisker is grown from the first electrically conductive surface, and is provided to be electrically conductive. Electrically insulative material is provided about the nanowhisker. An electrically conductive material is deposited over the electrically insulative material in electrical contact with the nanowhisker at a second elevation which is elevationally outward of the first elevation, and the electrically conductive material is provided into a second conductive structure. Other aspects and implementations are contemplated.

摘要翻译： 本发明包括电互连不同高程导电结构的方法，形成电容器的方法，在DRAM中形成衬底位线接触和位线之间的互连的方法，以及形成DRAM存储单元的方法。 在一个实施方式中，电连接不同高程导电结构的方法包括在衬底的第一高度处形成包括第一导电表面的第一导电结构。 纳米晶须从第一导电表面生长，并被提供为导电的。 提供关于纳米晶须的电绝缘材料。 导电材料沉积在电绝缘材料上，在第二高度处与纳米晶须电接触，第二高度位于第一高度的正上方，并且导电材料被提供到第二导电结构中。 考虑了其他方面和实现。

公开(公告)号：US07807535B2

公开(公告)日：2010-10-05

申请号：US11712151

申请日：2007-02-28

申请人： Nirmal Ramaswamy ,  Gurtej S. Sandhu ,  Chris M. Carlson ,  F. Daniel Gealy

发明人： Nirmal Ramaswamy ,  Gurtej S. Sandhu ,  Chris M. Carlson ,  F. Daniel Gealy

IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L21/20 ,  H01L21/338

CPC分类号： H01L29/66787 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02491 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/02658

摘要： The invention includes methods of forming layers comprising epitaxial silicon. In one implementation, an opening is formed within a first material received over a monocrystalline material. Opposing walls, of a second material, are formed within the opening which are laterally displaced inwardly of the opposing sidewalls, a space being received between the opposing walls and the opposing sidewalls, with monocrystalline material being exposed between the opposing walls within the opening. A silicon-comprising layer is epitaxially grown from the exposed monocrystalline material within the second material-lined opening. Other aspects and implementations are contemplated.

摘要翻译： 本发明包括形成包含外延硅的层的方法。 在一个实施方案中，在通过单晶材料接收的第一材料内形成开口。 第二材料的相对的壁形成在开口内，其横向位于相对的侧壁的内侧，空间容纳在相对的壁和相对的侧壁之间，单晶材料暴露在开口内的相对的壁之间。 在第二材料衬里的开口内从暴露的单晶材料外延生长含硅层。 考虑了其他方面和实现。

公开(公告)号：US20090244806A1

公开(公告)日：2009-10-01

申请号：US12480496

申请日：2009-06-08

申请人： Vishwanath Bhat ,  Noel Rocklein ,  F. Daniel Gealy

发明人： Vishwanath Bhat ,  Noel Rocklein ,  F. Daniel Gealy

IPC分类号： H01G4/008 ,  H01G9/00

CPC分类号： H01L28/60 ,  Y10T29/417

摘要： A method of forming a capacitor includes forming a conductive first capacitor electrode material comprising TiN over a substrate. TiN of the TiN-comprising material is oxidized effective to form conductive TiOxNy having resistivity no greater than 1 ohm·cm over the TiN-comprising material where x is greater than 0 and y is from 0 to 1.4. A capacitor dielectric is formed over the conductive TiOxNy. Conductive second capacitor electrode material is formed over the capacitor dielectric. Other aspects and implementations are contemplated, including capacitors independent of method of fabrication.

摘要翻译： 形成电容器的方法包括在衬底上形成包含TiN的导电的第一电容器电极材料。 含TiN的材料的TiN被有效地氧化以形成电阻率不大于1欧姆·厘米的电导率TiO x N y，其中x大于0且y为0至1.4。 在导电TiO x N y上形成电容器电介质。 在电容器电介质上形成导电的第二电容器电极材料。 考虑了其他方面和实现方式，包括独立于制造方法的电容器。

公开(公告)号：US20090195967A1

公开(公告)日：2009-08-06

申请号：US12422788

申请日：2009-04-13

申请人： Cancheepuram V. Srividya ,  Noel Rocklein ,  John Vernon ,  Jeff Nelson ,  F. Daniel Gealy ,  David Korn

发明人： Cancheepuram V. Srividya ,  Noel Rocklein ,  John Vernon ,  Jeff Nelson ,  F. Daniel Gealy ,  David Korn

IPC分类号： H01G4/06 ,  H01L29/92

CPC分类号： C23C16/405 ,  C23C16/40 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/3162 ,  H01L21/31641 ,  H01L21/31645 ,  H01L28/40

摘要： The invention includes ALD-type methods in which two or more different precursors are utilized with one or more reactants to form a material. In particular aspects, the precursors are hafnium and aluminum, the only reactant is ozone, and the material is hafnium oxide predominantly in a tetragonal crystalline phase.

摘要翻译： 本发明包括ALD型方法，其中使用两种或更多种不同的前体与一种或多种反应物形成材料。 在特定方面，前体是铪和铝，唯一的反应物是臭氧，并且该材料主要是四方晶相中的铪氧化物。

公开(公告)号：US07537804B2

公开(公告)日：2009-05-26

申请号：US11413466

申请日：2006-04-28

申请人： Cancheepuram V. Srividya ,  Noel Rocklein ,  John Vernon ,  Jeff Nelson ,  F. Daniel Gealy ,  David Korn

发明人： Cancheepuram V. Srividya ,  Noel Rocklein ,  John Vernon ,  Jeff Nelson ,  F. Daniel Gealy ,  David Korn

IPC分类号： C23C16/455

CPC分类号： C23C16/405 ,  C23C16/40 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/3162 ,  H01L21/31641 ,  H01L21/31645 ,  H01L28/40

摘要： In some embodiments, the invention may include utilization of at least one iteration of an ALD pulse sequence that has the pulse subsets M2-M1-R- and M1-(R-M2-)x: where x is at least 2; where M1 is a first metal-containing precursor comprising a first metal, M2 is a second metal-containing precursor comprising a second metal different from the first metal, and R is a reactant which reacts with one or both of the first and second metals. The ALD pulse sequence forms material over a substrate, and such material includes the first and second metals. The hyphen between pulses means that the second pulse directly follows the first pulse, with the term “directly follows” indicating that the second pulse either immediately follows the first pulse or that only a purge separates the first and second pulses.

摘要翻译： 在一些实施例中，本发明可以包括使用具有脉冲子集M2-M1-R-和M1-（R-M2-）x的ALD脉冲序列的至少一次迭代; 其中x至少为2; 其中M1是包含第一金属的第一含金属前体，M2是包含不同于第一金属的第二金属的第二含金属前体，R是与第一和第二金属中的一种或两种反应的反应物。 ALD脉冲序列在衬底上形成材料，并且这种材料包括第一和第二金属。 脉冲之间的连字符意味着第二脉冲直接跟随第一脉冲，术语“直接跟随”表示第二脉冲紧接在第一脉冲之后，或者只有清除分离第一和第二脉冲。

公开(公告)号：US07041570B2

公开(公告)日：2006-05-09

申请号：US10299145

申请日：2002-11-19

申请人： F. Daniel Gealy ,  Thomas M. Graettinger

发明人： F. Daniel Gealy ,  Thomas M. Graettinger

IPC分类号： H01L21/20

CPC分类号： H01L28/90 ,  H01G4/33 ,  H01L23/5223 ,  H01L28/55 ,  H01L28/65 ,  H01L28/84 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a capacitor is disclosed. The method includes forming a first substrate layer, and forming a first electrode on the first substrate layer. The first electrode includes at least one non-smooth surface and is formed from a material selected from the group consisting of transition metals, conductive oxides, alloys thereof, and combinations thereof. The method also includes forming a dielectric on the first electrode and the first substrate layer, and forming a second electrode on the dielectric and the first substrate layer. The second electrode includes at least one non-smooth surface. The method further includes forming a second substrate layer on the second electrode.

摘要翻译： 公开了形成电容器的方法。 该方法包括形成第一衬底层，并在第一衬底层上形成第一电极。 第一电极包括至少一个非光滑表面，并且由选自过渡金属，导电氧化物，其合金及其组合的材料形成。 该方法还包括在第一电极和第一衬底层上形成电介质，以及在电介质和第一衬底层上形成第二电极。 第二电极包括至少一个非光滑表面。 该方法还包括在第二电极上形成第二衬底层。