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    Low-Pin Microcontroller Device With Multiple Independent Microcontrollers
    1.
    发明申请
    Low-Pin Microcontroller Device With Multiple Independent Microcontrollers 有权
    具有多个独立微控制器的低引脚微控制器器件

    公开(公告)号：US20160267046A1

    公开(公告)日：2016-09-15

    申请号：US15064964

    申请日：2016-03-09

    Applicant: Microchip Technology Incorporated

    Inventor： Bryan Kris ,  Igor Wojewoda ,  Alex Dumais ,  Mike Catherwood ,  Brian Fall ,  Jason Tollefson ,  Calum Wilke ,  Dave Mickey ,  Thomas Spohrer

    IPC: G06F13/42 ,  G06F13/16 ,  G06F13/364

    CPC classification number: G06F13/4282 ,  G06F13/1673 ,  G06F13/364 ,  G06F13/385 ,  G06F15/7807 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

    Abstract: A microcontroller device has a housing with a plurality of external pins having a plurality of input/output pins, a first microcontroller with a first central processing unit (CPU), a first system bus coupled with the first CPU, first memory coupled with the first system bus, and a first plurality of peripheral devices coupled with the first system bus, a second microcontroller with a second central processing unit (CPU), a second system bus coupled with the second CPU, second memory coupled with the second system bus, and a second plurality of peripheral devices coupled with the second system bus, and a pad ownership multiplexer unit being controllable to assign control of the input/output pins to either the first microcontroller or the second microcontroller, wherein the number of external pins is less than the sum of a data buswidth of the first and second microcontroller.

    Abstract translation: 微控制器装置具有壳体，多个外部引脚具有多个输入/输出引脚，具有第一中央处理单元（CPU）的第一微控制器，与第一CPU耦合的第一系统总线，与第一中央处理单元 系统总线和与第一系统总线耦合的第一多个外围设备，具有第二中央处理单元（CPU）的第二微控制器，与第二CPU耦合的第二系统总线，与第二系统总线耦合的第二存储器，以及 与第二系统总线耦合的第二多个外围设备，以及焊盘所有权复用器单元，其可控制以将输入/输出引脚的控制分配给第一微控制器或第二微控制器，其中外部引脚的数量小于 第一和第二微控制器的数据总线宽度之和。

    Dithering circuit for serial data transmission
    2.
    发明授权
    Dithering circuit for serial data transmission 有权
    用于串行数据传输的抖动电路

    公开(公告)号：US09054851B2

    公开(公告)日：2015-06-09

    申请号：US14197812

    申请日：2014-03-05

    Applicant: Microchip Technology Incorporated

    Inventor： Stephen Bowling ,  Samar Naik ,  Igor Wojewoda

    IPC: H04L7/00 ,  H04L7/033 ,  H04L7/04 ,  H04L25/49

    CPC classification number: H04L7/0079 ,  H04L7/0331 ,  H04L7/044 ,  H04L25/49 ,  H04L25/4902

    Abstract: A system for determining a unit time of a serial transmission protocol, wherein the serial transmission protocol defines a unit time (UT) by transmitting a calibration pulse having a predetermined length of N*UT and wherein a receiver is operated by system clock, includes: a clock divider for dividing the system dock by M, wherein M evenly divides N, and a detector for sampling a received data nibble length by using a dithered sampling clock.

    Abstract translation: 一种用于确定串行传输协议的单位时间的系统，其中所述串行传输协议通过发送具有预定长度的N * UT的校准脉冲来定义单位时间（UT），并且其中接收机由系统时钟操作，包括： 用于将系统基座划分为M的时钟分频器，其中M均匀地划分N，以及用于使用抖动采样时钟对接收的数据半字节长度进行采样的检测器。

    Temperature compensated clock frequency monitor
    3.
    发明授权
    Temperature compensated clock frequency monitor 有权

    公开(公告)号：US10936004B2

    公开(公告)日：2021-03-02

    申请号：US16143967

    申请日：2018-09-27

    Applicant: Microchip Technology Incorporated

    Inventor： Bryan Kris ,  Igor Wojewoda ,  Stephen Bowling ,  Yong Yuenyongsgool

    IPC: G06F1/08 ,  G06F1/20 ,  G06F11/30 ,  G01R19/25 ,  G05B13/02 ,  G01R23/15 ,  H03L1/02 ,  G04G3/04 ,  G05B19/042

    Abstract: A temperature-compensating clock frequency monitor circuit may be provided to detect a clock pulse frequency in an electronic device that may cause erratic or dangerous operation of the device, as a function of an operating temperature of the device. The temperature-compensating clock frequency monitor circuit include a temperature sensor configured to measure a temperature associated with an electronic device, a clock having an operating frequency, and a frequency monitoring system. The frequency monitoring system may be configured to determine the operating frequency of the clock, and based at least on (a) the operating frequency of the clock and (b) the measured temperature associated with the electronic device, generate a corrective action signal to initiate a corrective action associated with the electronic device or a related device. The temperature sensor, clock, and frequency monitoring system may, for example, be provided on a microcontroller.

    ANALOG-TO-DIGITAL CONVERSION WITH MICRO-CODED SEQUENCER
    7.
    发明申请
    ANALOG-TO-DIGITAL CONVERSION WITH MICRO-CODED SEQUENCER 有权
    微型编码器的模拟数字转换

    公开(公告)号：US20160112060A1

    公开(公告)日：2016-04-21

    申请号：US14883842

    申请日：2015-10-15

    Applicant: Microchip Technology Incorporated

    Inventor： James E. Bartling ,  Igor Wojewoda ,  Kevin Kilzer

    IPC: H03M1/12 ,  G06F1/32

    CPC classification number: H03M1/12 ,  G06F1/32 ,  H03K17/9622 ,  H03K2217/960725 ,  H03M1/00 ,  H03M1/1225 ,  H03M1/1245 ,  H03M1/50

    Abstract: A micro-coded sequencer controls complex conversion sequences independent of a central processing unit (CPU). Micro-coding provides for easily adding new process steps and/or updating existing process steps. Such a programmable sequencer in combination with an analog-to-digital conversion module such as an analog-to-digital converter (ADC) or a charge time measurement unit (CTMU), and digital processing circuits may be configured to work independently of the CPU in combination with the micro-coded sequencer. Thereby providing self-sufficient operation in low power modes when the CPU and other high power modules are in a low power sleep mode. Such a peripheral can execute data collection and processing thereof, then wake the CPU only when needed, thereby saving power. Furthermore, this peripheral does not require CPU processing so that time critical applications that do require control by the CPU can operate more efficiently and with less operating overhead burden.

    Abstract translation: 微编码序列器控制独立于中央处理单元（CPU）的复杂转换序列。 微编码提供了轻松添加新的流程步骤和/或更新现有的流程步骤。 与诸如模数转换器（ADC）或充电时间测量单元（CTMU）之类的模数转换模块和数字处理电路组合的这种可编程序排序器可被配置为独立于CPU 与微编码序列器结合使用。 因此，当CPU和其他高功率模块处于低功耗睡眠模式时，能够以低功耗模式提供自给自足的操作。 这样的外设可以执行数据收集和处理，然后在需要时唤醒CPU，从而节省电力。 此外，该外设不需要CPU处理，因此要求CPU进行控制的时间关键应用程序可以更有效地运行，同时减少运营负担。

    Dual Boot Panel SWAP Mechanism
    9.
    发明申请
    Dual Boot Panel SWAP Mechanism 有权
    双引导板SWAP机制

    公开(公告)号：US20140281465A1

    公开(公告)日：2014-09-18

    申请号：US14204208

    申请日：2014-03-11

    Applicant: Microchip Technology Incorporated

    Inventor： Michael I. Catherwood ,  Brant Ivey ,  Igor Wojewoda ,  David Mickey ,  Joseph Kanellopoulos

    IPC: G06F9/44

    CPC classification number: G06F9/4401 ,  G06F8/656 ,  G06F9/441

    Abstract: A central processing unit with dual boot capabilities is disclosed comprising an instruction memory further comprising a first and second memory area which are configured to be individually programmable, wherein first and second memory area can be assigned to an active memory from which instructions are executed and an inactive memory, respectively. The instruction set for the central processing unit comprises a dedicated instruction that allows to perform a swap from the an active memory area to an inactive memory area, wherein the swap is performed by executing the dedicated instruction in the active memory followed by a program flow change instruction in the active memory, whereupon the inactive memory becomes the new active memory and the active memory becomes the new inactive memory and execution of instructions continues in the new active memory.

    Abstract translation: 公开了一种具有双引导功能的中央处理单元，包括指令存储器，进一步包括被配置为可单独编程的第一和第二存储器区域，其中第一和第二存储器区域可被分配给执行指令的有效存储器， 不活动内存。 用于中央处理单元的指令集包括允许执行从活动存储器区域到非活动存储器区域的交换的专用指令，其中通过在活动存储器中执行专用指令执行交换，随后进行程序流程改变 指令在活动存储器中，因此非活动存储器变为新的活动存储器，并且活动存储器变为新的非活动存储器，并且新的活动存储器中的指令的执行继续。

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