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12 条记录 (耗时 0.022 秒)

    Plasma treatment device
    1.
    发明申请
    Plasma treatment device 审中-公开
    等离子体处理装置

    公开(公告)号：US20070158027A1

    公开(公告)日：2007-07-12

    申请号：US11702075

    申请日：2007-02-05

    申请人： Makoto Aoki ,  Hikaru Yoshitaka ,  Yoshihiro Kato ,  Shigeo Ashigaki ,  Syoichi Abe

    发明人： Makoto Aoki ,  Hikaru Yoshitaka ,  Yoshihiro Kato ,  Shigeo Ashigaki ,  Syoichi Abe

    IPC分类号： C23F1/00 ,  C23C16/00

    CPC分类号： H01J37/32623 ,  H01J37/32633

    摘要： In a parallel plate type plasma processing apparatus (1), a baffle plate (28) is fitted between a ceiling (2b) and side wall (2a) of a chamber (2). The baffle plate (28) confines plasma into the upper portion of the chamber (2), and at the same time, constitutes a return route of a return current to a high frequency power source (27). A return current flowing through the baffle plate (28) returns to the high frequency power source (27) via the ceiling (2b) of the chamber (2).

    摘要翻译： 在平行板式等离子体处理装置（1）中，挡板（28）装配在室（2）的顶板（2b）和侧壁（2a）之间。 挡板（28）将等离子体限制在室（2）的上部，并且同时构成返回电流返回到高频电源（27）的返回路径。 流经挡板（28）的回流电流通过腔室（2）的顶板（2b）返回到高频电源（27）。

    Peeling-off method and reworking method of resist film
    4.
    发明申请
    Peeling-off method and reworking method of resist film 审中-公开
    抗剥离膜剥离方法及修复方法

    公开(公告)号：US20070184379A1

    公开(公告)日：2007-08-09

    申请号：US10591345

    申请日：2005-03-01

    申请人： Shigeo Ashigaki ,  Yoshihiro Kato ,  Yoshihiro Hirota ,  Yusuke Muraki ,  Tetsu Kawasaki ,  Satoru Shimura

    发明人： Shigeo Ashigaki ,  Yoshihiro Kato ,  Yoshihiro Hirota ,  Yusuke Muraki ,  Tetsu Kawasaki ,  Satoru Shimura

    IPC分类号： G03C1/00

    CPC分类号： G03F7/42 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/67051

    摘要： A processing method of a substrate includes: a step of forming an Si—C based film and a resist film in turn on an objective film to be etched that has been formed on a substrate; a first etching step of etching the Si—C based film making use of the resist film as a mask; and a second etching step of etching the objective film to be etched making use of the resist film and the Si—C based film as a mask. The processing method further includes a peeling-off step of peeling-off the resist film at a desired timing. The peeling-off step includes a preparing step of preparing an organic solvent as a release agent, and an applying step of applying the organic solvent to the resist film.

    摘要翻译： 基板的处理方法包括：依次形成Si-C基膜和抗蚀剂膜的步骤，所述Si-C基膜和抗蚀剂膜依次形成在基板上形成的待蚀刻目标膜上; 蚀刻使用抗蚀剂膜作为掩模的Si-C基膜的第一蚀刻步骤; 以及使用抗蚀剂膜和Si-C基膜作为掩模蚀刻待蚀刻的目标膜的第二蚀刻步骤。 该处理方法还包括在期望的时刻剥离抗蚀剂膜的剥离步骤。 剥离步骤包括制备作为脱模剂的有机溶剂的制备步骤和将有机溶剂施加到抗蚀剂膜的施加步骤。

    METHOD OF INTEGRATING METAL-CONTAINING FILMS INTO SEMICONDUCTOR DEVICES
    7.
    发明申请
    METHOD OF INTEGRATING METAL-CONTAINING FILMS INTO SEMICONDUCTOR DEVICES 失效
    将含金属膜整合到半导体器件中的方法

    公开(公告)号：US20080119033A1

    公开(公告)日：2008-05-22

    申请号：US11561810

    申请日：2006-11-20

    申请人： Shigeo Ashigaki ,  Hideaki Yamasaki ,  Tomoyuki Sakoda ,  Mikio Suzuki ,  Genji Nakamura ,  Gert Leusink

    发明人： Shigeo Ashigaki ,  Hideaki Yamasaki ,  Tomoyuki Sakoda ,  Mikio Suzuki ,  Genji Nakamura ,  Gert Leusink

    IPC分类号： H01L21/28

    CPC分类号： H01L21/28079 ,  H01L29/4958 ,  H01L29/513 ,  H01L29/518

    摘要： A method for integrating a metal-containing film in a semiconductor device, for example a gate stack. In one embodiment, the method includes providing a substrate in a process chamber, depositing the tungsten-containing film on the substrate at a first substrate temperature by exposing the substrate to a deposition gas containing a tungsten carbonyl precursor, heat treating the tungsten-containing film at a second substrate temperature greater than the first substrate temperature to remove carbon monoxide gas from the tungsten-containing film, and forming a barrier layer on the heat treated tungsten-containing film. Examples of tungsten-containing films include W, WN, WSi, and WC. Additional embodiments include depositing metal-containing films containing Ni, Mo, Co, Rh, Re, Cr, or Ru from the corresponding metal carbonyl precursors.

    摘要翻译： 一种用于将含金属膜整合在半导体器件例如栅极堆叠中的方法。 在一个实施例中，该方法包括在处理室中提供衬底，通过将衬底暴露于含有羰基钨前体的沉积气体，在第一衬底温度下将含钨膜沉积在衬底上，热处理含钨膜 在大于第一衬底温度的第二衬底温度下从含钨膜中除去一氧化碳气体，并在热处理的含钨膜上形成阻挡层。 含钨膜的实例包括W，WN，WSi和WC。 另外的实施方案包括从相应的金属羰基前体沉积含有Ni，Mo，Co，Rh，Re，Cr或Ru的含金属膜。

    Method of integrating metal-containing films into semiconductor devices
    8.
    发明授权
    Method of integrating metal-containing films into semiconductor devices 失效
    将含金属膜整合到半导体器件中的方法

    公开(公告)号：US07674710B2

    公开(公告)日：2010-03-09

    申请号：US11561810

    申请日：2006-11-20

    申请人： Shigeo Ashigaki ,  Hideaki Yamasaki ,  Tomoyuki Sakoda ,  Mikio Suzuki ,  Genji Nakamura ,  Gert Leusink

    发明人： Shigeo Ashigaki ,  Hideaki Yamasaki ,  Tomoyuki Sakoda ,  Mikio Suzuki ,  Genji Nakamura ,  Gert Leusink

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/28079 ,  H01L29/4958 ,  H01L29/513 ,  H01L29/518

    摘要： A method for integrating a metal-containing film in a semiconductor device, for example a gate stack. In one embodiment, the method includes providing a substrate in a process chamber, depositing the tungsten-containing film on the substrate at a first substrate temperature by exposing the substrate to a deposition gas containing a tungsten carbonyl precursor, heat treating the tungsten-containing film at a second substrate temperature greater than the first substrate temperature to remove carbon monoxide gas from the tungsten-containing film, and forming a barrier layer on the heat treated tungsten-containing film. Examples of tungsten-containing films include W, WN, WSi, and WC. Additional embodiments include depositing metal-containing films containing Ni, Mo, Co, Rh, Re, Cr, or Ru from the corresponding metal carbonyl precursors.

    摘要翻译： 一种用于将含金属膜整合在半导体器件例如栅极堆叠中的方法。 在一个实施例中，该方法包括在处理室中提供衬底，通过将衬底暴露于含有羰基钨前体的沉积气体，在第一衬底温度下将含钨膜沉积在衬底上，热处理含钨膜 在大于第一衬底温度的第二衬底温度下从含钨膜中除去一氧化碳气体，并在热处理的含钨膜上形成阻挡层。 含钨膜的实例包括W，WN，WSi和WC。 另外的实施方案包括从相应的金属羰基前体沉积含有Ni，Mo，Co，Rh，Re，Cr或Ru的含金属膜。

    Process of making and process of trimming a fuse in a top level metal and in a step
    9.
    发明授权
    Process of making and process of trimming a fuse in a top level metal and in a step 失效
    制造和加工在顶级金属中修整保险丝的步骤

    公开(公告)号：US5650355A

    公开(公告)日：1997-07-22

    申请号：US473386

    申请日：1995-06-07

    申请人： Hideyuki Fukuhara ,  Shigeo Ashigaki

    发明人： Hideyuki Fukuhara ,  Shigeo Ashigaki

    IPC分类号： H01L21/82 ,  H01L23/525 ,  H01L21/44

    CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  Y10S148/055 ,  Y10S438/926

    摘要： A fuse link 16 is formed of a portion of a top level of patterned metal conductor in a multilevel conductor integrated circuit 10. A deposited layer of oxide material 26 covers the fuse link. Radiant energy from such as a laser 36 is directed through the oxide material 26 to heat and open the fuse link 16. Layers of deposited protective oxide 28 and PIX 30 then cover the fuse link and layer of oxide material. One photoprocessing step is avoided by locating the fuse link 16 and bond pad 22, both made from the top layer of conductive material, at different levels. The blanket etch then exposes the bond pad 22 while leaving the fuse link 16 covered. The fuse link can be formed down in a step 38 or the bond pad 22 can be formed above such as a group of memory cells 80. The bond pad 22 and fuse link 16 also can be formed at the same level with other process procedures.

    摘要翻译： 熔丝连接16由多层导体集成电路10中的图案化金属导体顶层的一部分形成。氧化物材料26的沉积层覆盖熔丝链。 来自诸如激光器36的辐射能量被引导通过氧化物材料26以加热并打开熔丝16。沉积的保护氧化物28和PIX 30的层然后覆盖熔丝链和氧化物层。 通过将熔丝连接16和两个由导电材料的顶层制成的接合焊盘22放置在不同的水平上来避免一个光处理步骤。 毯式蚀刻然后暴露接合焊盘22，同时保留熔丝链16。 熔丝链可以在步骤38中向下形成，或者可以在诸如一组存储单元80的上方形成接合焊盘22.接合焊盘22和熔丝连接16也可以与其它工艺程序形成在相同的水平。

    Fuse in top level metal and in a step, process of making and process of trimming
    10.
    发明授权
    Fuse in top level metal and in a step, process of making and process of trimming 失效
    保险丝在顶级金属和一步，制作和加工修整过程

    公开(公告)号：US06331739B1

    公开(公告)日：2001-12-18

    申请号：US08804850

    申请日：1997-02-24

    申请人： Hideyuki Fukuhara ,  Shigeo Ashigaki

    发明人： Hideyuki Fukuhara ,  Shigeo Ashigaki

    IPC分类号： H01L2978

    CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  Y10S148/055 ,  Y10S438/926 ,  H01L2924/00

    摘要： A fuse link 16 is formed of a portion of a top level of patterned metal conductor in a multilevel conductor integrated circuit 10. A deposited layer of oxide material 26 covers the fuse link. Radiant energy from such as a laser 36 is directed through the oxide material 26 to heat and open the fuse link 16. Layers of deposited protective oxide 28 and PIX 30 then cover the fuse link and layer of oxide material. One photoprocessing step is avoided by locating the fuse link 16 and bond pad 22, both made from the top layer of conductive material, at different levels. The blanket etch then exposes the bond pad 22 while leaving the fuse link 16 covered. The fuse link can be formed down in a step 38 or the bond pad 22 can be formed above such as a group of memory cells 80. The bond pad 22 and fuse link 16 also can be formed at the same level with other process procedures.

    摘要翻译： 熔丝连接16由多层导体集成电路10中的图案化金属导体顶层的一部分形成。氧化物材料26的沉积层覆盖熔丝链。 来自诸如激光器36的辐射能量被引导通过氧化物材料26以加热并打开熔丝16。沉积的保护氧化物28和PIX 30的层然后覆盖熔丝链和氧化物层。 通过将熔丝连接16和两个由导电材料的顶层制成的接合焊盘22放置在不同的水平上来避免一个光处理步骤。 毯式蚀刻然后暴露接合焊盘22，同时保留熔丝链16。 熔丝链可以在步骤38中向下形成，或者可以在诸如一组存储单元80的上方形成接合焊盘22.接合焊盘22和熔丝连接16也可以与其它工艺程序形成在相同的水平。