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    Thin film multi-layer structure and method for manufacturing the same
    2.
    发明授权
    Thin film multi-layer structure and method for manufacturing the same 失效
    薄膜多层结构及其制造方法

    公开(公告)号：US5618636A

    公开(公告)日：1997-04-08

    申请号：US404881

    申请日：1995-03-16

    申请人： Manabu Watanabe ,  Kazuaki Satoh

    发明人： Manabu Watanabe ,  Kazuaki Satoh

    IPC分类号： B32B27/34 ,  H01L23/498 ,  H01L23/538 ,  H05K1/00 ,  H05K1/02 ,  H05K3/46 ,  B32B15/08 ,  H05K1/03

    CPC分类号： H01L23/5383 ,  B32B27/34 ,  H01L23/49894 ,  H05K1/0271 ,  H05K3/467 ,  H05K3/4688 ,  H01L2924/0002 ,  H05K2201/0154 ,  H05K2201/068 ,  H05K3/4676 ,  Y10T428/12569 ,  Y10T428/12986 ,  Y10T428/31681

    摘要： A thin film multi-layer structure includes a plurality of metal thin film layers, and a plurality of layers made of polyimide. The plurality of metal thin film layers and the plurality of layers made of polyimide are stacked in a predetermined order, the plurality of layers made of polyimide being grouped into a first group and a second group including at least a layer located at a top of the plurality of layers. A Young's modulus value of the polyimide of which each layer in the second group is made is less than that of the polyimide of which each layer in the first group is made and a thermal expansion coefficient of the polyimide of which each layer in the first group is made is less than that of the polyimide of which each layer in the second group is made.

    摘要翻译： 薄膜多层结构包括多个金属薄膜层和由聚酰亚胺制成的多层。 多个金属薄膜层和由聚酰亚胺制成的多个层以预定顺序层叠，由聚酰亚胺制成的多个层分成第一组，第二组至少包括位于第一组顶部的层 多层。 制造第二组中每层的聚酰亚胺的杨氏模量值小于制备第一组中每层的聚酰亚胺的杨氏模量值，以及第一组中每层的聚酰亚胺的热膨胀系数 被制成小于其中制成第二组中每层的聚酰亚胺。

    Single-chip memory system including buffer
    3.
    发明授权
    Single-chip memory system including buffer 失效
    单片存储系统包括缓冲区

    公开(公告)号：US6085297A

    公开(公告)日：2000-07-04

    申请号：US905730

    申请日：1997-08-04

    申请人： Kazuaki Satoh

    发明人： Kazuaki Satoh

    IPC分类号： G06F12/00 ,  G06F9/38 ,  G06F12/08

    CPC分类号： G06F9/3802 ,  G06F9/3824

    摘要： To operate faster, a memory system includes a central processing unit (CPU) for executing a first instruction, and for outputting first, second and third signals, a memory device for storing first data and the first instruction, a first buffer for storing second data, a controller for writing the second data into the memory device when the controller receives the first signal, for reading the first data from the memory device after writing the second data into the memory device when the controller receives the second signal, and for reading the first instruction from the memory device and sending the first instruction to the CPU before writing the second data into the memory device when the controller receives the third signal.

    摘要翻译： 为了更快地操作，存储器系统包括用于执行第一指令的中央处理单元（CPU），并且用于输出第一，第二和第三信号，用于存储第一数据和第一指令的存储器件，用于存储第二数据的第一缓冲器 控制器，当所述控制器接收到所述第一信号时，将所述第二数据写入所述存储器件，以在所述控制器接收到所述第二信号时将所述第二数据写入所述存储器件之后从所述存储器件读取所述第一数据，并且用于读取所述第二数据 当所述控制器接收到所述第三信号时，将所述第二数据写入所述存储器件之前，将所述第一指令发送到所述CPU。

    METHOD OF MANUFACTURING VERTICAL MAGNETIC HEAD
    4.
    发明申请
    METHOD OF MANUFACTURING VERTICAL MAGNETIC HEAD 审中-公开
    制造垂直磁头的方法

    公开(公告)号：US20090266705A1

    公开(公告)日：2009-10-29

    申请号：US12333075

    申请日：2008-12-11

    申请人： Kentaro Suzuki ,  Kazuaki Satoh

    发明人： Kentaro Suzuki ,  Kazuaki Satoh

    IPC分类号： B44C1/22

    CPC分类号： G11B5/3116 ,  G11B5/1278 ,  G11B5/3163

    摘要： The method of manufacturing a vertical magnetic head comprises the steps of: forming a resist pattern including a concave section on a wafer substrate; laminating a plurality of films in the concave section until forming a prescribed multilayer structure of the main magnetic pole; and removing the resist pattern. Inner faces of the concave section are perpendicular to a surface of the wafer substrate. The laminating step includes the sub-steps of: (a) performing a sputtering process, in which particles are perpendicularly sputtered with respect to the surface of the wafer substrate, a plurality of times so as to laminate a plurality of sputtered films in the concave section; and (b) removing the sputtered films, which have been stuck on the resist pattern in the sub-step (a), from the resist pattern. The sub-steps (a) and (b) are repeated until the prescribed multilayer structure is formed.

    摘要翻译： 制造垂直磁头的方法包括以下步骤：在晶片衬底上形成包括凹部的抗蚀剂图案; 在凹部中层叠多个膜直到形成规定的主磁极的多层结构; 并去除抗蚀剂图案。 凹部的内表面垂直于晶片基板的表面。 层压步骤包括以下子步骤：（a）进行溅射工艺，其中相对于晶片基板的表面垂直溅射颗粒，以使多个溅射膜层叠在凹面中 部分; 和（b）从抗蚀剂图案中去除已经粘附在子步骤（a）中的抗蚀剂图案上的溅射膜。 重复子步骤（a）和（b），直到形成规定的多层结构。

    Method of producing double-sided circuit board
    5.
    发明授权
    Method of producing double-sided circuit board 失效
    生产双面电路板的方法

    公开(公告)号：US06526654B1

    公开(公告)日：2003-03-04

    申请号：US09606008

    申请日：2000-06-29

    申请人： Zhiyi Song ,  Kiyokazu Moriizumi ,  Kazuaki Satoh ,  Norikazu Ozaki

    发明人： Zhiyi Song ,  Kiyokazu Moriizumi ,  Kazuaki Satoh ,  Norikazu Ozaki

    IPC分类号： H05K334

    CPC分类号： H01L23/5383 ,  H01L21/481 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K1/113 ,  H05K3/0035 ,  H05K3/4605 ,  H05K2201/0154 ,  H05K2201/09436 ,  H05K2201/096 ,  H05K2201/10318 ,  H05K2203/1581 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  H01L2924/00

    摘要： The method comprises forming a plurality of wiring pattern layers on the front surface of a substrate. In the process of forming the wiring pattern layers, an insulator protection film keeps covering over the wiring pattern on the back surface of the substrate. When the formation of the wiring pattern layers has been completed on the front surface of the substrate, a penetrating hole is bored in the cured or hardened insulator protection film. The penetrating hole may be utilized as a conductive via or a conductive through hole. A wiring pattern layer is then formed over the hardened insulator protection film on the back surface of the substrate. It is possible to omit an additional process for removing the insulator protection film. The method contributes to further facilitation of production process and further reduction in production cost.

    摘要翻译： 该方法包括在基板的前表面上形成多个布线图案层。 在形成布线图案层的过程中，绝缘体保护膜保持覆盖在基板的背面上的布线图案上。 当在基板的前表面上完成布线图形层的形成时，在固化或硬化的绝缘体保护膜中钻出一个穿透孔。 穿透孔可以用作导电通孔或导电通孔。 然后在基板的背面上的硬化的绝缘体保护膜上形成布线图案层。 可以省略用于去除绝缘体保护膜的附加工艺。 该方法有助于进一步促进生产过程，进一步降低生产成本。

    Multi-layer film substrate and process for production thereof
    8.
    发明授权
    Multi-layer film substrate and process for production thereof 失效
    多层膜基材及其制造方法

    公开(公告)号：US5908529A

    公开(公告)日：1999-06-01

    申请号：US460896

    申请日：1995-06-05

    申请人： Kazuaki Satoh

    发明人： Kazuaki Satoh

    IPC分类号： H05K3/46 ,  B32B27/34 ,  C08G73/02 ,  C08G73/06 ,  H05K1/00 ,  H05K3/38 ,  C09J11/04

    CPC分类号： B32B27/34 ,  C08G73/0213 ,  C08G73/0611 ,  C08G73/0627 ,  H05K3/4676 ,  Y10T428/259 ,  Y10T428/2852

    摘要： A multi-layer film substrate comprising at least two laminated insulating layers composed of a polyimide having a low thermal expansion, wherein an adhesion layer composed of an Si-containing or SiO.sub.2 -dispersed polyimide is interposed between the low thermal expansion polyimide layers. The substrate is produced by laminating at least two insulating layers composed of a polyimide having a low thermal expansion, wherein the low thermal expansion polyimide layers are laminated through an adhesion layer composed of an Si-containing or SiO.sub.2 -dispersed polyimide.

    摘要翻译： 一种多层膜基材，包括由具有低热膨胀性的聚酰亚胺组成的至少两层叠绝缘层，其中由含Si或SiO2分散的聚酰亚胺组成的粘合层介于低热膨胀聚酰亚胺层之间。 通过层叠由热膨胀率低的聚酰亚胺构成的至少两层绝缘层来制造基板，其中通过由含Si或SiO2分散的聚酰亚胺构成的粘合层层叠低热膨胀聚酰亚胺层。

    Multi-chip module having thermal contacts
    9.
    发明授权
    Multi-chip module having thermal contacts 失效
    具有热触点的多芯片模块

    公开(公告)号：US5432675A

    公开(公告)日：1995-07-11

    申请号：US151871

    申请日：1993-11-15

    申请人： Haruo Sorimachi ,  Kiyotaka Seyama ,  Makoto Sumiyoshi ,  Kazuaki Satoh

    发明人： Haruo Sorimachi ,  Kiyotaka Seyama ,  Makoto Sumiyoshi ,  Kazuaki Satoh

    IPC分类号： H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H05K7/20

    CPC分类号： H01L23/49894 ,  H01L23/3677 ,  H01L23/49866 ,  H01L23/538 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/16195 ,  H01L2924/19107 ,  H01L2924/3011

    摘要： A multi-chip module (MCM) having semiconductor chips on a top surface of multi-layered interconnection circuits formed on a planar surface of a substrate including: (a) multi-layered interconnection circuits comprising alternatively laminated interconnection layers with insulating layers, and thermal contacts, each of the thermal contacts comprising successively laminated interconnection layers on a bottom and on side-walls of a vertical hole penetrating a plurality of the insulating layers, and a thermal conductor filling the vertical hole on the successively laminated interconnection layers, and (b) a plurality of the semiconductor chips attached to the thermal conductor. In a preferred embodiment, a V-shaped vertical hole is formed in the insulating layers of polyimide for a thermal contact, copper films are successively laminated thereon, unpatterned copper and gold films are deposited thereon, and the entire surface of the metal film including the hole is coated by a silver-powder containing epoxy film, to which semiconductor chips are adhered.

    摘要翻译： 一种多芯片模块（MCM），其在多层互连电路的顶面上形成半导体芯片，所述多层布线电路形成在基板的平面上，所述多层布线电路的平面表面包括：（a）多层互连电路， 触点，每个热触头包括穿透多个绝缘层的垂直孔的底部和侧壁上的相继层压的互连层，以及填充连续层压的互连层上的垂直孔的热导体，和（b ）附接到热导体的多个半导体芯片。 在优选实施例中，在聚酰亚胺的绝缘层中形成V形垂直孔用于热接触，铜膜依次层压在其上，未图案化的铜和金膜沉积在其上，金属膜的整个表面包括 孔被含有银粉的环氧树脂膜涂覆，半导体芯片被粘附到其上。

    Method of producing thin film multi-layered substrate
    10.
    发明授权
    Method of producing thin film multi-layered substrate 失效
    制造薄膜多层基板的方法

    公开(公告)号：US5422228A

    公开(公告)日：1995-06-06

    申请号：US100964

    申请日：1993-08-03

    申请人： Kazuaki Satoh

    发明人： Kazuaki Satoh

    IPC分类号： H05K3/46 ,  G03F7/11 ,  H01L21/48 ,  H01L21/768 ,  H05K3/38 ,  G03C5/00

    CPC分类号： H05K3/385 ,  H01L21/4857 ,  H01L21/76886 ,  G03F7/11 ,  H05K3/4644

    摘要： A method of producing a thin film multi-layered substrate involving the steps of subjecting a copper wiring formed on a substrate to chromate treatment with an aqueous solution containing potassium bichromate or sodium bichromate as a principal component and containing chromic anhydride blended therewith, forming an interlevel insulating film consisting of photosensitive polyimide on the copper wiring, and exposing and developing the photosensitive polyimide film to form a pattern. A miniature pattern can be formed at a high speed and with high production yield.

    摘要翻译： 一种制造薄膜多层基板的方法，包括以下步骤：使形成在基板上的铜布线用含有重铬酸钾或重铬酸钠的水溶液作为主要成分进行铬酸盐处理，并含有与其混合的铬酸酐，形成层间 在铜布线上由光敏聚酰亚胺构成的绝缘膜，以及曝光和显影感光性聚酰亚胺膜以形成图案。 可以高速，高产量地形成微型图案。